公开(公告)号：US20190319617A1

公开(公告)日：2019-10-17

申请号：US16375233

申请日：2019-04-04

Applicant: STMicroelectronics S.r.l.

Inventor： Francesco Pulvirenti ,  Salvatore Cassata ,  Salvatore Giuseppe Privitera

IPC: H03K17/687 ,  H03K17/16 ,  G01R19/00

Abstract: A dead-time circuit includes a signal propagation path from a first input node receiving a PWM modulated control signal to an output node, such signal propagation path switchable between a non-conductive state and a conductive state, such that the signal at the first input node is transferred to the output node when the signal propagation path is in the conductive state. The dead-time circuit further includes a differentiator circuit block coupled to a second input node and to the signal propagation path, the second input node configured to be coupled to an intermediate node of a half-bridge circuit. The differentiator circuit block switches the signal propagation path between the non-conductive state and the conductive state as a function of a time derivative of a signal at the second input node. At least one time-delay circuit component delays transfer of the signal at the first input node to the output node.

公开(公告)号：US09237039B2

公开(公告)日：2016-01-12

申请号：US14307098

申请日：2014-06-17

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Salvatore Cassata ,  Francesco Pulvirenti ,  Salvatore Giuseppe Privitera

IPC: H03K3/00 ,  H04L25/02 ,  H04B3/00 ,  H02H9/04

CPC classification number: H04L25/0292 ,  H02H9/04 ,  H04B3/00 ,  H04L25/028 ,  Y10T29/49169

Abstract: A transceiver is connectable to a cable with at least three wires. The transceiver may include a controlled output stage including a high-side leg, having two P-type transistors coupled in series and having a common current terminal, coupled between an output pin and a positive supply pin. The P-type transistors have body regions coupled to the common current terminal of the high-side leg. A low-side leg, includes two N-type transistors coupled in series and having a common current terminal, coupled between the output pin and a negative supply pin. The N-type transistors have body regions coupled to the common current terminal of the low-side leg. The protection circuit also includes a voltage clamper coupled between the common current terminals.

Abstract translation: 收发器可连接至具有至少三根电线的电缆。 收发器可以包括受控的输出级，包括高侧支路，具有耦合在输出引脚和正电源引脚之间的具有串联耦合并具有公共电流端子的两个P型晶体管。 P型晶体管具有耦合到高侧支腿的公共电流端子的主体区域。 低侧支腿包括串联耦合并具有公共电流端子的两个N型晶体管，耦合在输出引脚和负电源引脚之间。 N型晶体管具有耦合到低侧支腿的公共电流端子的主体区域。 保护电路还包括耦合在公共电流端子之间的电压钳位器。

公开(公告)号：US10720921B2

公开(公告)日：2020-07-21

申请号：US16375233

申请日：2019-04-04

Applicant: STMicroelectronics S.r.l.

Inventor： Francesco Pulvirenti ,  Salvatore Cassata ,  Salvatore Giuseppe Privitera

IPC: H02M3/337 ,  H03K17/687 ,  G01R19/00 ,  H03K17/16

Abstract: A dead-time circuit includes a signal propagation path from a first input node receiving a PWM modulated control signal to an output node, such signal propagation path switchable between a non-conductive state and a conductive state, such that the signal at the first input node is transferred to the output node when the signal propagation path is in the conductive state. The dead-time circuit further includes a differentiator circuit block coupled to a second input node and to the signal propagation path, the second input node configured to be coupled to an intermediate node of a half-bridge circuit. The differentiator circuit block switches the signal propagation path between the non-conductive state and the conductive state as a function of a time derivative of a signal at the second input node. At least one time-delay circuit component delays transfer of the signal at the first input node to the output node.