-
公开(公告)号：US20240195294A1
公开(公告)日：2024-06-13
申请号：US18432576
申请日：2024-02-05
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Pulvirenti
IPC: H02M3/07
CPC classification number: H02M3/07
Abstract: In an embodiment, a voltage multiplier comprises an input node, an output node, and first and second control nodes for receiving first and second clock signals defining two commutation states. An ordered sequence of intermediate nodes is coupled between the input and output nodes and includes two ordered sub-sequences. Capacitors are coupled: between each odd intermediate node in the first sub-sequence and the first control node; between each even intermediate node in the first sub-sequence and the second control node; between each odd intermediate node in the second sub-sequence and a corresponding odd intermediate node in the first sub-sequence; and between each even intermediate node in the second sub-sequence and a corresponding even intermediate node in the first sub-sequence. The circuit comprises selectively conductive electronic components coupled to the intermediate nodes.
-
公开(公告)号：US11451130B2
公开(公告)日：2022-09-20
申请号：US17229554
申请日：2021-04-13
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Fabrizio Bognanni , Giovanni Caggegi , Giuseppe Cantone , Vincenzo Marano , Francesco Pulvirenti
IPC: H02M1/08 , H02M3/07 , H02M3/158 , H03K17/687
Abstract: A circuit includes a current path and a negative bootstrap circuitry coupled to the current path. The current path is coupled between a floating voltage and a reference ground, and includes a current generator coupled through a resistor to the floating voltage at a first node of the current generator. The current generator is controlled by a pulse signal. The negative bootstrap circuitry includes a pump capacitor coupled to a second node of the current generator and to the reference ground. The pump capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.
-
公开(公告)号：US11881759B2
公开(公告)日：2024-01-23
申请号：US17888001
申请日：2022-08-15
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Fabrizio Bognanni , Giovanni Caggegi , Giuseppe Cantone , Vincenzo Marano , Francesco Pulvirenti
IPC: H02M1/08 , H02M3/07 , H02M3/158 , H03K17/687
CPC classification number: H02M1/08 , H02M3/07 , H02M3/158 , H03K17/6872 , H03K2217/0081
Abstract: A circuit includes a current path and a negative bootstrap circuitry coupled to the current path. The current path is coupled between a floating voltage and a reference ground, and includes a current generator coupled through a resistor to the floating voltage at a first node of the current generator. The current generator is controlled by a pulse signal. The negative bootstrap circuitry includes a pump capacitor coupled to a second node of the current generator and to the reference ground. The pump capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.
-
公开(公告)号：US11791815B2
公开(公告)日：2023-10-17
申请号：US17959785
申请日：2022-10-04
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Giovanni Fontana , Marco Riva , Francesco Pulvirenti , Giuseppe Cantone
IPC: H03K5/151 , H03K17/16 , H03K17/687 , H03K17/06 , H03K17/0812
CPC classification number: H03K17/063 , H03K17/08122 , H03K2217/0063 , H03K2217/0072 , H03K2217/0081
Abstract: A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.
-
公开(公告)号：US20220006450A1
公开(公告)日：2022-01-06
申请号：US17355055
申请日：2021-06-22
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Giovanni Fontana , Marco Riva , Francesco Pulvirenti , Giuseppe Cantone
IPC: H03K17/06 , H03K17/0812
Abstract: A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.
-
Patent Agency Ranking
公开(公告)号：US10547171B2
公开(公告)日：2020-01-28
申请号：US15596465
申请日：2017-05-16
Applicant: STMicroelectronics S.r.l.
Inventor： Ignazio Bruno Mirabella , Francesco Pulvirenti , Salvatore Pappalardo
IPC: H02H9/02 , H02H7/00 , H03K17/082
Abstract: A power transistor supplying power to a load is coupled to a current limiter circuit including a differential amplifier that operates to detect a difference between a sense voltage, indicative of a load current, and a voltage reference. A control terminal of the power transistor is driven by a first output of the differential amplifier as a function of the detected difference. A voltage clamp circuit coupled to an input terminal generates a floating ground. A short-circuit protection circuit coupled to the floating ground and interposed between a second output of the differential amplifier and the control terminal of the power transistor provides a short-circuit protection for the first output of the differential amplifier. A reaction time circuit is coupled between the first and second outputs of the differential amplifier and a source terminal of the power transistor to limit a short-circuit current at the source terminal.
-
公开(公告)号：US09356587B2
公开(公告)日：2016-05-31
申请号：US14622322
申请日：2015-02-13
Applicant: STMicroelectronics S.r.l.
Inventor： Ignazio Bruno Mirabella , Francesco Pulvirenti
CPC classification number: H03K5/125 , H03K5/2436
Abstract: A high voltage comparison circuit includes an input stage generating an intermediate signal as a result of a comparison between an input signal and a first voltage reference and an output stage configured to generate an output signal referenced to a second voltage reference (different from the first voltage reference) in response to the intermediate signal.
Abstract translation: 高电压比较电路包括作为输入信号和第一参考电压之间的比较的结果产生中间信号的输入级和被配置为产生参考第二参考电压的输出信号（不同于第一电压 参考）响应于中间信号。
-
8.发明授权Low drop out voltage regulator with operational transconductance amplifier and related method of generating a regulated voltage 有权具有工作跨导放大器的低压降稳压器及产生调节电压的相关方法公开(公告)号：US09223329B2
公开(公告)日：2015-12-29
申请号：US14097796
申请日：2013-12-05
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Francesco Pulvirenti , Santo Ilardo
Abstract: A low drop out voltage regulator includes an operational transconductance amplifier configured to be supplied with a supply voltage of the regulator, receive as inputs a reference voltage and a feedback voltage, and generate an intermediate current based upon a difference between the reference voltage and the feedback voltage. A current-to-voltage amplification stage is configured to be supplied with a boosted voltage greater than the supply voltage from a high voltage line, receive as input the intermediate current, and generate a driving voltage that is changed based upon the intermediate current. A pass transistor is controlled with the driving voltage to keep constant on a second conduction terminal thereof a regulated output voltage. A feedback network generates the feedback voltage based on the regulated output voltage.
Abstract translation: 低压差稳压器包括：运算跨导放大器，被配置为提供调节器的电源电压，接收参考电压和反馈电压作为输入，并且基于参考电压和反馈之间的差产生中间电流 电压。 电流 - 电压放大级被配置为被提供大于来自高压线的电源电压的升压电压，作为输入接收中间电流，并且产生基于中间电流而改变的驱动电压。 通过驱动电压来控制传输晶体管，以在其第二导通端子上保持恒定的稳定的输出电压。 反馈网络基于稳压输出电压产生反馈电压。
-
公开(公告)号：US11929674B2
公开(公告)日：2024-03-12
申请号：US17732281
申请日：2022-04-28
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Pulvirenti
IPC: H02M3/07
CPC classification number: H02M3/07
Abstract: In an embodiment, a voltage multiplier comprises an input node, an output node, and first and second control nodes for receiving first and second clock signals defining two commutation states. An ordered sequence of intermediate nodes is coupled between the input and output nodes and includes two ordered sub-sequences. Capacitors are coupled: between each odd intermediate node in the first sub-sequence and the first control node; between each even intermediate node in the first sub-sequence and the second control node; between each odd intermediate node in the second sub-sequence and a corresponding odd intermediate node in the first sub-sequence; and between each even intermediate node in the second sub-sequence and a corresponding even intermediate node in the first sub-sequence. The circuit comprises selectively conductive electronic components coupled to the intermediate nodes.
-
公开(公告)号：US20220393579A1
公开(公告)日：2022-12-08
申请号：US17732281
申请日：2022-04-28
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Pulvirenti
IPC: H02M3/07
Abstract: In an embodiment, a voltage multiplier comprises an input node, an output node, and first and second control nodes for receiving first and second clock signals defining two commutation states. An ordered sequence of intermediate nodes is coupled between the input and output nodes and includes two ordered sub-sequences. Capacitors are coupled: between each odd intermediate node in the first sub-sequence and the first control node; between each even intermediate node in the first sub-sequence and the second control node; between each odd intermediate node in the second sub-sequence and a corresponding odd intermediate node in the first sub-sequence; and between each even intermediate node in the second sub-sequence and a corresponding even intermediate node in the first sub-sequence. The circuit comprises selectively conductive electronic components coupled to the intermediate nodes.
-
-
-
-
-
-
-
-
-
Search Results
21
records
(took 0.023 seconds)
