公开(公告)号：US20150243356A1

公开(公告)日：2015-08-27

申请号：US14623300

申请日：2015-02-16

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS PTE LTD

Inventor： Antonino CONTE ,  Alberto Jose' DI MARTINO ,  Kailash KHAIRNAR

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C8/04 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0061 ,  G11C13/0097 ,  G11C2213/79

Abstract: A phase change non-volatile memory device has a memory array with a plurality of memory cells arranged in rows and columns, a column decoder and a row decoder designed to select columns, and, respectively, rows of the memory array during operations of programming of corresponding memory cells. A control logic, coupled to the column decoder and the row decoder, is designed to execute a sequential programming command, to control the column decoder and row decoder to select one column of the memory array and execute sequential programming operations on a desired block of memory cells belonging to contiguous selected rows of the selected column.

Abstract translation: 相变非易失性存储器件具有存储器阵列，其具有排列成行和列的多个存储器单元，列解码器和行解码器，被设计为在编程操作期间选择列以及分别存储器阵列的行 相应的存储单元。 耦合到列解码器和行解码器的控制逻辑被设计为执行顺序编程命令，以控制列解码器和行解码器来选择存储器阵列的一列并对期望的存储块执行顺序编程操作 属于所选列的连续选定行的单元格。