公开(公告)号：US20040252571A1

公开(公告)日：2004-12-16

申请号：US10894286

申请日：2004-07-19

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Francois Hugues ,  Philippe Roche

IPC: G11C005/00

CPC classification number: H03K19/00338 ,  H03K19/0075

Abstract: A circuit (200) for protection against voltage or current spikes receives an initial clock signal (CI) and transmits at least one resultant clock signal (CN1, CN2, CP1, CP2) to a downstream circuit. This resultant clock signal is inactive if a random voltage or current spike appears upstream. This averts the possibility of disturbing the operation of the downstream circuit. Application to the protection of clock circuits for integrated circuits.

Abstract translation: 用于防止电压或电流尖峰的电路（200）接收初始时钟信号（CI），并将至少一个合成时钟信号（CN1，CN2，CP1，CP2）发送到下游电路。 如果随机电压或电流尖峰出现在上游，则该合成时钟信号无效。 这避免了干扰下游电路的操作的可能性。 应用于集成电路的时钟电路保护。

公开(公告)号：US20030214772A1

公开(公告)日：2003-11-20

申请号：US10191089

申请日：2002-07-09

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Francois Hugues ,  Philippe Roche ,  Richard Ferrant

IPC: H01H073/00

CPC classification number: H03K19/00338 ,  H03K19/0075

Abstract: A circuit (200) for protection against voltage or current spikes receives an initial clock signal (CI) and transmits at least one resultant clock signal (CN1, CN2, CP1, CP2) to a downstream circuit. This resultant clock signal is inactive if a random voltage or current spike appears upstream. This averts the possibility of disturbing the operation of the downstream circuit. Application to the protection of clock circuits for integrated circuits.

Abstract translation: 用于防止电压或电流尖峰的电路（200）接收初始时钟信号（CI），并将至少一个合成时钟信号（CN1，CN2，CP1，CP2）发送到下游电路。 如果随机电压或电流尖峰出现在上游，则该合成时钟信号无效。 这避免了干扰下游电路的操作的可能性。 应用于集成电路的时钟电路保护。