公开(公告)号：US20010043728A1

公开(公告)日：2001-11-22

申请号：US09877440

申请日：2001-06-08

Applicant: STMicroelectronics, Inc.

Inventor： Alan Kramer ,  James Brady

IPC: G06K009/00

CPC classification number: G06K9/0002

Abstract: A scanning fingerprint detection system includes an array of capacitive sensing elements, the array having a first dimension greater than the width of a fingerprint and a second dimension less than the length of a fingerprint. Each of the capacitive sensing elements has first and second conductor plates connected across an inverting amplifier, the conductor plates forming capacitors with the ridges and valleys of a fingerprint of a finger pressed against a protective coating above the array, the inverting amplifier generating a signal indicative of a ridge or valley. Circuitry is provided for scanning the array to capture an image of a portion of fingerprint and for assembling the captured images into a fingerprint image.

Abstract translation: 扫描指纹检测系统包括电容感测元件阵列，该阵列具有大于指纹宽度的第一尺寸和小于指纹长度的第二维度。 每个电容感测元件具有连接在反相放大器上的第一和第二导体板，导体板形成电容器，其中脊和指纹的指纹压在阵列上方的保护涂层上，反相放大器产生指示信号 一个山脊或山谷。 提供电路用于扫描阵列以捕获一部分指纹的图像并将捕获的图像组装成指纹图像。

公开(公告)号：US20020113251A1

公开(公告)日：2002-08-22

申请号：US09790370

申请日：2001-02-21

Applicant: STMicroelectronics, Inc.

Inventor： James Brady

IPC: H01L031/109

CPC classification number: G11C29/848 ,  G11C8/10

Abstract: A memory device having redundancy is disclosed. The memory device includes an array of memory cells organized into rows and columns of memory cells, each row of memory cells including a plurality of addressable memory cells and redundant memory cells, the array of memory cells including row lines and column lines, each row line being coupled to memory cells in a distinct row of memory cells, each column line being coupled to memory cells in a distinct column of memory cells, and column input/output lines. The memory device further includes a redundancy circuitry for selectively coupling column lines to column input/output lines of the array of memory cells and selectively decoupling at least one column line from the column input/output lines, based upon an address value received by the memory device during a memory access operation.

Abstract translation: 公开了一种具有冗余性的存储器件。 存储器件包括组织成存储器单元的行和列的存储器单元的阵列，每行存储单元包括多个可寻址存储器单元和冗余存储器单元，存储单元阵列包括行线和列线，每行行 耦合到存储器单元的不同行中的存储器单元，每个列线耦合到存储器单元的不同列中的存储器单元以及列输入/输出线。 存储器件还包括冗余电路，用于将列线选择性地耦合到存储器单元阵列的列输入/输出线，并且基于由存储器接收的地址值，选择性地将至少一列列线与列输入/输出线相分离 设备在存储器访问操作期间。