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300 条记录 (耗时 0.024 秒)

    Semiconductor light-emitting device and method for fabricating the same
    2.
    发明申请
    Semiconductor light-emitting device and method for fabricating the same 失效
    半导体发光器件及其制造方法

    公开(公告)号：US20040191938A1

    公开(公告)日：2004-09-30

    申请号：US10817800

    申请日：2004-04-06

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Daisuke Ueda ,  Shinichi Takigawa

    IPC分类号： H01L031/109

    CPC分类号： B82Y20/00 ,  H01L33/145 ,  H01L33/32 ,  H01S5/2214 ,  H01S5/2215 ,  H01S5/34333

    摘要： An n-type buffer layer composed of n-type GaN, an n-type cladding layer composed of n-type AlGaN, an n-type optical confinement layer composed of n-type GaN, a single quantum well active layer composed of undoped GaInN, a p-type optical confinement layer composed of p-type GaN, a p-type cladding layer composed of p-type AlGaN, and a p-type contact layer composed of p-type GaN are formed on a substrate composed of sapphire. A current blocking layer formed in an upper portion of the p-type cladding layer and on both sides of the p-type contact layer to define a ridge portion is composed of a dielectric material obtained by replacing some of nitrogen atoms composing a Group III-V nitride semiconductor with oxygen atoms.

    摘要翻译： 由n型GaN构成的n型缓冲层，由n型AlGaN构成的n型覆盖层，由n型GaN构成的n型光限制层，由未掺杂的GaInN构成的单量子阱活性层 在由蓝宝石构成的基板上形成由p型GaN构成的p型光限制层，由p型AlGaN构成的p型覆盖层和由p型GaN构成的p型接触层。 形成在p型覆层的上部并且在p型接触层的两侧形成脊部的电流阻挡层由通过将构成III- 具有氧原子的氮化物半导体。

    Ferroelectric memory devices having an expanded plate electrode and methods for fabricating the same
    3.
    发明申请
    Ferroelectric memory devices having an expanded plate electrode and methods for fabricating the same 失效
    具有发泡板电极的铁电存储器件及其制造方法

    公开(公告)号：US20040169202A1

    公开(公告)日：2004-09-02

    申请号：US10787424

    申请日：2004-02-26

    发明人： Hyun-Yul Kang ,  Yoon-Jong Song ,  Nak-Won Jang

    IPC分类号： H01L031/109

    CPC分类号： G11C11/22 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507

    摘要： Ferroelectric memory devices are formed on an integrated circuit substrate. A bottom interlayer dielectric layer is positioned on the integrated circuit substrate and a plurality of ferroelectric capacitors are arranged in a row and column relationship on the bottom interlayer dielectric layer. A top interlayer dielectric layer is disposed on a surface of the integrated circuit substrate including the plurality of ferroelectric capacitors. The top interlayer dielectric layer includes via holes disposed on and associated with ones of the ferroelectric capacitors. A plate electrode is formed in the top interlayer dielectric layer. The plate electrode extends into respective ones of the via holes to contact top surfaces of at least two neighboring ones of the plurality of ferroelectric capacitors. Methods or fabricating ferroelectric memory devices are also provided

    摘要翻译： 铁电存储器件形成在集成电路衬底上。 底层间介质层位于集成电路基板上，并且多个铁电电容器以行和列关系布置在底层间介质层上。 在包括多个铁电电容器的集成电路基板的表面上设置顶层间介质层。 顶层间介质层包括布置在铁电电容器之一上并与其相关联的通孔。 在顶层间介质层中形成平板电极。 板电极延伸到相应的通孔中以接触多个铁电电容器中的至少两个相邻的电介质电容器的顶表面。 还提供了方法或制造铁电存储器件

    Thin film circuit
    4.
    发明申请
    Thin film circuit 审中-公开
    薄膜电路

    公开(公告)号：US20040135174A1

    公开(公告)日：2004-07-15

    申请号：US10752000

    申请日：2004-01-07

    申请人： Semiconductor Energy Laboratory Co., Ltd, a Japan corporation

    发明人： Shunpei Yamazaki ,  Jun Koyama ,  Hisashi Ohtani

    IPC分类号： H01L031/109

    CPC分类号： H01L29/04 ,  H01L21/02532 ,  H01L21/02672 ,  H01L27/12 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675

    摘要： A practical operational amplifier circuit is formed using thin film transistors. An operational amplifier circuit is formed by thin film transistors formed on a quartz substrate wherein 90% or more of n-channel type thin film transistors have mobility at a value of 260 cm2/Vs or more and wherein 90% or more of p-channel type thin film transistors have mobility at a value of 150 cm2/Vs or more. The thin film transistors have active layers formed using a crystalline silicon film fabricated using a metal element that promoted crystallization of silicon. The crystalline silicon film is a collection of a multiplicity of elongate crystal structures extending in a certain direction, and the above-described characteristics can be achieved by matching the extending direction and the moving direction of carriers.

    摘要翻译： 使用薄膜晶体管形成实际的运算放大器电路。 运算放大电路由形成在石英基板上的薄膜晶体管形成，其中n沟道型薄膜晶体管的90％以上的迁移率为260cm 2 / Vs以上，其中90％以上的 p沟道型薄膜晶体管的迁移率为150cm 2 / Vs以上。 薄膜晶体管具有使用使用促进硅结晶的金属元素制造的晶体硅膜形成的有源层。 结晶硅膜是沿一定方向延伸的多个细长晶体结构的集合，并且可以通过匹配载流子的延伸方向和移动方向来实现上述特性。

    Semiconductor device
    5.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20040124440A1

    公开(公告)日：2004-07-01

    申请号：US10701511

    申请日：2003-11-06

    发明人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Takeshi Sakata ,  Shinichi Miyatake ,  Hiromasa Noda ,  Kazuhiko Kajigaya

    IPC分类号： H01L031/109

    CPC分类号： G11C11/4096 ,  G11C11/4076 ,  G11C2207/002 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/10897

    摘要： A column select line YS1 can be enabled at the same time as the enabling of a word line. Write data is written from an I/O gate into a selected data line. An adjacent unselected sense amplifier reads data from memory cells. A source node of a cross-coupled sense amplifier connected to each data line pair is divided for each column select line, thereby to prevent a write-selected cross-coupled amplifier from driving the source node. In the write operation, data can be written at a high speed. On the other hand, it becomes possible to prevent a write-sense amplifier from driving the source node. Therefore, adjacent sense amplifiers can achieve stable read operation without being affected from the write-sense amplifier.

    摘要翻译： 可以在启用字线的同时启用列选择线YS1。 写数据从I / O门写入选定的数据线。 相邻的未选择的读出放大器从存储器单元读取数据。 连接到每个数据线对的交叉耦合读出放大器的源节点被划分用于每个列选择线，从而防止写入选择的交叉耦合放大器驱动源节点。 在写入操作中，可以高速写入数据。 另一方面，可以防止写入读出放大器驱动源节点。 因此，相邻的读出放大器可以实现稳定的读取操作，而不受写入读出放大器的影响。

    Planarizers for spin etch planarization of electronic components and methods of use thereof
    6.
    发明申请
    Planarizers for spin etch planarization of electronic components and methods of use thereof 审中-公开
    用于电子部件的自旋蚀刻平面化的平面化器及其使用方法

    公开(公告)号：US20040124438A1

    公开(公告)日：2004-07-01

    申请号：US10444700

    申请日：2003-05-22

    发明人： Shyama Mukherjee ,  Joseph Levert ,  Donald BeBear

    IPC分类号： H01L031/109

    CPC分类号： H01L21/7684 ,  H01L21/32115 ,  H01L21/3212 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electronic component contemplated comprises a) a substrate layer, b) a dielectric layer coupled to the substrate layer, c) a barrier layer coupled to the dielectric layer, d) a conductive layer coupled to the barrier layer, and e) a protective layer coupled to the conductive layer. The electronic component contemplated herein can be produced by a) providing a substrate; b) coupling a dielectric layer to the substrate; c) coupling a barrier layer to the dielectric layer; d) coupling a conductive layer to the barrier layer; and e) coupling a protective layer to the conductive layer. The protective layer may then be cured to a desirable hardness. A method of planarizing a conductive surface of an electronic component may comprise a) introducing or coupling a protective layer onto a conductive layer; b) dispersing the protective layer across the conductive layer; c) curing the protective layer; d) introducing an etching solution onto the conductive layer; and e) etching the conductive surface to substantial planarity.

    摘要翻译： 构成的电子部件包括：a）基底层，b）耦合到该基底层的电介质层，c）与该介电层耦合的阻挡层，d）与阻挡层耦合的导电层，和e）保护层 耦合到导电层。 本文考虑的电子部件可以通过以下方式制备：a）提供基底; b）将介电层耦合到所述衬底; c）将阻挡层耦合到电介质层; d）将导电层耦合到阻挡层; 以及e）将保护层耦合到所述导电层。 然后可以将保护层固化至所需的硬度。 平面化电子部件的导电表面的方法可以包括：a）将保护层引入或耦合到导电层上; b）将保护层分散在导电层上; c）固化保护层; d）在导电层上引入蚀刻溶液; 以及e）将所述导电表面蚀刻到基本的平坦度。

    Method and apparatus for reducing fixed charge in semiconductor device layers
    8.
    发明申请
    Method and apparatus for reducing fixed charge in semiconductor device layers 失效
    用于减少半导体器件层中的固定电荷的方法和装置

    公开(公告)号：US20040119096A1

    公开(公告)日：2004-06-24

    申请号：US10727889

    申请日：2003-12-04

    申请人： Micron Technology, Inc.

    发明人： Ravi Iyer ,  Randhir P. S. Thakur ,  Howard E. Rhodes

    IPC分类号： H01L031/109

    CPC分类号： H01L21/02164 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/31625

    摘要： The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.

    摘要翻译： 通过使诸如TEOS的有机前体与O 3反应，沉积在半导体器件上的硼磷硅玻璃绝缘膜中的固定电荷被还原。 当在高于约480摄氏度的温度下完成时，所得膜中的碳水平似乎降低，导致场晶体管器件的阈值电压更高。