公开(公告)号：US20180315666A1

公开(公告)日：2018-11-01

申请号：US16027707

申请日：2018-07-05

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN ,  Yann MIGNOT

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49 ,  H01L29/417 ,  H01L21/02 ,  H01L29/165 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US20150155176A1

公开(公告)日：2015-06-04

申请号：US14094858

申请日：2013-12-03

Applicant: STMicroelectronics, Inc. ,  Lam Research Corporation

Inventor： Yann MIGNOT ,  Bhaskar NAGABHIRAVA

IPC: H01L21/3065 ,  H01L27/04 ,  H01L21/308

CPC classification number: H01L27/04 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

Abstract: A method and integrated circuit structure. The method includes reducing sidewall height nonuniformity in sidewall image transfer processes by depositing an organic planarization layer over the integrated circuit structure after sidewall definition, mandrel removal, and etch of exposed portions of a first underlying layer in a sidewall image transfer process that is thick enough to cover one or more first sidewalls having a first height and one or more second sidewalls having a second height with the first height greater than the second height, removing a part of the organic planarization layer leaving a first depth of the one or more first sidewalls exposed, removing the exposed first depth of the one or more first sidewalls, and removing the remaining organic planarization layer.

Abstract translation: 一种方法和集成电路结构。 该方法包括通过在侧壁限定，心轴移除以及在足够厚的侧壁图像转移过程中第一下层的暴露部分的蚀刻之后，在集成电路结构上沉积有机平坦化层来减少侧壁图像转移过程中的侧壁高度不均匀性 以覆盖具有第一高度的一个或多个第一侧壁和具有第二高度的一个或多个第二侧壁，第二高度具有大于第二高度的第一高度，去除一部分有机平坦化层，留下一个或多个第一侧壁的第一深度 暴露，去除一个或多个第一侧壁的暴露的第一深度，以及去除剩余的有机平坦化层。

公开(公告)号：US20190304845A1

公开(公告)日：2019-10-03

申请号：US16445778

申请日：2019-06-19

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN ,  Yann MIGNOT

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49 ,  H01L21/762 ,  H01L29/417 ,  H01L21/02 ,  H01L29/165 ,  H01L27/092

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.