公开(公告)号：US08828882B2

公开(公告)日：2014-09-09

申请号：US13713135

申请日：2012-12-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Arnaud Tournier ,  Françcois Leverd

IPC: H01L21/302 ,  H01L21/461 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3065

CPC classification number: H01L21/30655 ,  H01L21/76237 ,  H01L29/0649

Abstract: A trench is formed in a semiconductor substrate by depositing an etch mask on the substrate having an opening, etching of the trench through the opening, and doping the walls of the trench. The etching step includes a first phase having an etch power set to etch the substrate under the etch mask, and a second phase having an etch power set smaller than the power of the first phase. Further, the doping of the walls of the trench is applied through the opening of the etch mask.

Abstract translation: 通过在具有开口的衬底上沉积蚀刻掩模，通过开口蚀刻沟槽以及掺杂沟槽的壁，在半导体衬底中形成沟槽。 蚀刻步骤包括具有蚀刻功能的第一相，其蚀刻蚀刻掩模下的衬底，以及具有小于第一相的功率的蚀刻功率集的第二相。 此外，通过蚀刻掩模的开口施加沟槽的壁的掺杂。