公开(公告)号：US08828882B2

公开(公告)日：2014-09-09

申请号：US13713135

申请日：2012-12-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Arnaud Tournier ,  Françcois Leverd

IPC: H01L21/302 ,  H01L21/461 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3065

CPC classification number: H01L21/30655 ,  H01L21/76237 ,  H01L29/0649

Abstract: A trench is formed in a semiconductor substrate by depositing an etch mask on the substrate having an opening, etching of the trench through the opening, and doping the walls of the trench. The etching step includes a first phase having an etch power set to etch the substrate under the etch mask, and a second phase having an etch power set smaller than the power of the first phase. Further, the doping of the walls of the trench is applied through the opening of the etch mask.

Abstract translation: 通过在具有开口的衬底上沉积蚀刻掩模，通过开口蚀刻沟槽以及掺杂沟槽的壁，在半导体衬底中形成沟槽。 蚀刻步骤包括具有蚀刻功能的第一相，其蚀刻蚀刻掩模下的衬底，以及具有小于第一相的功率的蚀刻功率集的第二相。 此外，通过蚀刻掩模的开口施加沟槽的壁的掺杂。

公开(公告)号：US11417789B2

公开(公告)日：2022-08-16

申请号：US16825298

申请日：2020-03-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Arnaud Tournier ,  Boris Rodrigues Goncalves ,  Francois Roy

IPC: H01L31/107 ,  H01L27/146

Abstract: An electronic device is provided that includes a photodiode. The photodiode includes a semiconductor region coupled to a node of application of a first voltage, and at least one semiconductor wall. The at least one semiconductor wall extends along at least a height of the photodiode and partially surrounds the semiconductor region.

公开(公告)号：US09087872B2

公开(公告)日：2015-07-21

申请号：US14168167

申请日：2014-01-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent Favennec ,  Arnaud Tournier ,  François Roy

IPC: H01L21/762 ,  H01L27/146

CPC classification number: H01L21/76224 ,  H01L21/76237 ,  H01L27/1463

Abstract: A structure comprising at least one DTI-type insulating trench in a substrate, the trench being at the periphery of at least one active area of the substrate forming a pixel, the insulating trench including a cavity filled with a dielectric material, the internal walls of the cavity being covered with a layer made of a boron-doped material.

Abstract translation: 一种结构，其包括在衬底中的至少一个DTI型绝缘沟槽，所述沟槽位于形成像素的衬底的至少一个有源区域的外围，所述绝缘沟槽包括填充有电介质材料的腔体， 该腔被由硼掺杂材料制成的层覆盖。

公开(公告)号：US11107938B2

公开(公告)日：2021-08-31

申请号：US16789997

申请日：2020-02-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Boris Rodrigues Goncalves ,  Arnaud Tournier

IPC: H01L31/0352 ,  H01L27/146 ,  H01L31/02 ,  H01L31/0203

Abstract: A photodiode include a first substrate layer of a first dopant type and a second substrate layer of a second dopant type on top of the first substrate layer. Semiconductor walls are provided in a semiconductor substrate which includes the first and second substrate layers. The semiconductor walls include: two outer semiconductor walls and at least one inside semiconductor wall positioned between the two outer semiconductor walls. Each inside semiconductor wall is located between two semiconductor walls having longer length.

公开(公告)号：US20140145251A1

公开(公告)日：2014-05-29

申请号：US14168167

申请日：2014-01-30

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Laurent Favennec ,  Arnaud Tournier ,  François Roy

IPC: H01L21/762 ,  H01L27/146

CPC classification number: H01L21/76224 ,  H01L21/76237 ,  H01L27/1463

Abstract: A structure comprising at least one DTI-type insulating trench in a substrate, the trench being at the periphery of at least one active area of the substrate forming a pixel, the insulating trench including a cavity filled with a dielectric material, the internal walls of the cavity being covered with a layer made of a boron-doped material.

Abstract translation: 一种结构，其包括在衬底中的至少一个DTI型绝缘沟槽，所述沟槽位于形成像素的衬底的至少一个有源区域的外围，所述绝缘沟槽包括填充有电介质材料的腔体， 该腔被由硼掺杂材料制成的层覆盖。

公开(公告)号：US11923465B2

公开(公告)日：2024-03-05

申请号：US17125654

申请日：2020-12-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Arnaud Tournier ,  Boris Rodrigues Goncalves ,  Frederic Lalanne

IPC: H01L31/02 ,  H01L27/146

CPC classification number: H01L31/02019 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/1463 ,  H01L31/02005 ,  H01L27/14643

Abstract: The present disclosure concerns a photodiode including at least one memory area, each memory area including at least two charge storage regions.

公开(公告)号：US20130154051A1

公开(公告)日：2013-06-20

申请号：US13713135

申请日：2012-12-13

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Arnaud Tournier ,  François Leverd

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/30655 ,  H01L21/76237 ,  H01L29/0649

Abstract: A trench is formed in a semiconductor substrate by depositing an etch mask on the substrate having an opening, etching of the trench through the opening, and doping the walls of the trench. The etching step includes a first phase having an etch power set to etch the substrate under the etch mask, and a second phase having an etch power set smaller than the power of the first phase. Further, the doping of the walls of the trench is applied through the opening of the etch mask.

Abstract translation: 通过在具有开口的衬底上沉积蚀刻掩模，通过开口蚀刻沟槽以及掺杂沟槽的壁，在半导体衬底中形成沟槽。 蚀刻步骤包括具有蚀刻功能的第一相，其蚀刻蚀刻掩模下的衬底，以及具有小于第一相的功率的蚀刻功率集的第二相。 此外，通过蚀刻掩模的开口施加沟槽的壁的掺杂。