公开(公告)号：US20240201873A1

公开(公告)日：2024-06-20

申请号：US18531044

申请日：2023-12-06

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Fabien ARRIVE ,  Yves MAGNAUD

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0655 ,  G06F3/0679

Abstract: A device executes an authentication process protected by an authentication counter that is incremented in case of an authentication failure. The incrementation of the counter is protected against unexpected device power-off or power-off attacks. A non-volatile memory is divided into pairs of cells. The protecting includes writing a fixed value D into an active pair of two consecutive cells. As long as successful authentications occur, the content of the first cell is overwritten by a random value. When a failed authentication occurs, the content of the second cell is overwritten by a random value and the next two consecutive cells are written with the fixed value D. Those cells form the active pair and the protection process is repeated. This mechanism facilitates preventing the lack of incrementation of the authentication counter in case of unexpected device power-off during the processing of a failed authentication.