公开(公告)号：US20170269156A1

公开(公告)日：2017-09-21

申请号：US15071342

申请日：2016-03-16

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Bruno Fel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318547 ,  G01R31/318563

Abstract: A scan chain for testing a combinatorial logic circuit includes a first scan chain path of flip-flops connected to the combinatorial logic circuit for functional mode operation during runtime of the combinatorial logic circuit. A second scan chain path of flip-flops is also connected to the combinatorial logic circuit and supports both a shift mode and a capture mode. The second scan chain path operates in shift mode while the first scan chain path is connected to the combinatorial logic circuit for functional mode operation. The second scan chain is then connected to the combinatorial logic circuit when run time is interrupted and operates in capture mode to apply the test data to the combinatorial logic circuit.

公开(公告)号：US10598728B2

公开(公告)日：2020-03-24

申请号：US15867285

申请日：2018-01-10

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Bruno Fel

IPC: G01R31/3177 ,  G01R31/3185

Abstract: A scan chain for testing a combinatorial logic circuit includes a first scan chain path of flip-flops connected to the combinatorial logic circuit for functional mode operation during runtime of the combinatorial logic circuit. A second scan chain path of flip-flops is also connected to the combinatorial logic circuit and supports both a shift mode and a capture mode. The second scan chain path operates in shift mode while the first scan chain path is connected to the combinatorial logic circuit for functional mode operation. The second scan chain is then connected to the combinatorial logic circuit when run time is interrupted and operates in capture mode to apply the test data to the combinatorial logic circuit.

公开(公告)号：US20180128876A1

公开(公告)日：2018-05-10

申请号：US15867285

申请日：2018-01-10

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Bruno Fel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318547 ,  G01R31/318563

Abstract: A scan chain for testing a combinatorial logic circuit includes a first scan chain path of flip-flops connected to the combinatorial logic circuit for functional mode operation during runtime of the combinatorial logic circuit. A second scan chain path of flip-flops is also connected to the combinatorial logic circuit and supports both a shift mode and a capture mode. The second scan chain path operates in shift mode while the first scan chain path is connected to the combinatorial logic circuit for functional mode operation. The second scan chain is then connected to the combinatorial logic circuit when run time is interrupted and operates in capture mode to apply the test data to the combinatorial logic circuit.

公开(公告)号：US09897653B2

公开(公告)日：2018-02-20

申请号：US15071342

申请日：2016-03-16

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Bruno Fel

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318547 ,  G01R31/318563

Abstract: A scan chain for testing a combinatorial logic circuit includes a first scan chain path of flip-flops connected to the combinatorial logic circuit for functional mode operation during runtime of the combinatorial logic circuit. A second scan chain path of flip-flops is also connected to the combinatorial logic circuit and supports both a shift mode and a capture mode. The second scan chain path operates in shift mode while the first scan chain path is connected to the combinatorial logic circuit for functional mode operation. The second scan chain is then connected to the combinatorial logic circuit when run time is interrupted and operates in capture mode to apply the test data to the combinatorial logic circuit.