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公开(公告)号：US20210265949A1
公开(公告)日：2021-08-26
申请号：US17180748
申请日：2021-02-20
Abstract: An embodiment of the present disclosure relates to a device comprising an electronic circuit; an oscillation circuit comprising a quartz crystal, configured to provide a clock signal to the electronic circuit; and a heater configured to increase the temperature of the quartz crystal.
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公开(公告)号：US10102171B2
公开(公告)日：2018-10-16
申请号：US15608857
申请日：2017-05-30
Inventor： Daniele Mangano , Ignazio Antonino Urzi
Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.
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公开(公告)号：US11764731B2
公开(公告)日：2023-09-19
申请号：US18059812
申请日：2022-11-29
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS , STMicroelectronics S.r.l.
CPC classification number: H03B5/36 , G06F1/10 , H03F3/245 , H04B1/0475 , H03B2200/004 , H03F2200/451 , H04B2001/0408
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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公开(公告)号：US11239796B2
公开(公告)日：2022-02-01
申请号：US17180748
申请日：2021-02-20
Abstract: An embodiment of the present disclosure relates to a device comprising an electronic circuit; an oscillation circuit comprising a quartz crystal, configured to provide a clock signal to the electronic circuit; and a heater configured to increase the temperature of the quartz crystal.
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公开(公告)号：US20230087239A1
公开(公告)日：2023-03-23
申请号：US18059812
申请日：2022-11-29
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS , STMicroelectronics S.r.l.
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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Patent Agency Ranking
公开(公告)号：US11496170B2
公开(公告)日：2022-11-08
申请号：US17180751
申请日：2021-02-20
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Abstract: The present disclosure relates to a method for controlling a device comprising an oscillation circuit, configured to provide a clock signal to a radio frequency circuit, and an antenna, in which the enabling of the passage of the signal from the circuit to the antenna is delayed with respect to an instant from which a power amplifier of the circuit is enabled.
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公开(公告)号：US10019399B2
公开(公告)日：2018-07-10
申请号：US14940026
申请日：2015-11-12
Inventor： Daniele Mangano , Ignazio Antonino Urzi
IPC: G06F17/50 , G06F13/36 , H04L12/933 , G06F15/78 , H04L12/935 , G06F13/40
CPC classification number: G06F13/36 , G06F13/4068 , G06F15/7807 , G06F15/7825 , G06F17/5077 , G06F2217/04 , G06F2217/06 , H04L49/109 , H04L49/15 , H04L49/3009
Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
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公开(公告)号：US20170270070A1
公开(公告)日：2017-09-21
申请号：US15608857
申请日：2017-05-30
Inventor： Daniele Mangano , Ignazio Antonino Urzi
CPC classification number: G06F13/4027 , G06F13/14 , G06F15/7825 , G06F2213/0038 , H04Q2213/13399 , H04Q2213/399
Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.
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公开(公告)号：US09697161B2
公开(公告)日：2017-07-04
申请号：US14219850
申请日：2014-03-19
Inventor： Daniele Mangano , Ignazio Antonino Urzi
CPC classification number: G06F13/4027 , G06F13/14 , G06F15/7825 , G06F2213/0038 , H04Q2213/13399 , H04Q2213/399
Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.
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公开(公告)号：US20160070667A1
公开(公告)日：2016-03-10
申请号：US14940026
申请日：2015-11-12
Inventor： Daniele Mangano , Ignazio Antonino Urzi
CPC classification number: G06F13/36 , G06F13/4068 , G06F15/7807 , G06F15/7825 , G06F17/5077 , G06F2217/04 , G06F2217/06 , H04L49/109 , H04L49/15 , H04L49/3009
Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
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