公开(公告)号：US20210409030A1

公开(公告)日：2021-12-30

申请号：US17352849

申请日：2021-06-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno GAILHARD ,  Laurent TRUPHEMUS ,  Christophe EVA

IPC: H03L7/10 ,  H03L7/089 ,  H03L7/099

Abstract: A start-up phase of a phase lock loop (PLL) circuit includes supplying, by a phase comparator, of control pulses during which an output signal frequency of an oscillator increases. The increase includes an application of a pre-charge current at the oscillator input. A determination is made of a time variation of the output signal frequency. At least one adjustment is made of the intensity of the pre-charge current depending on the at least one determined time variation so as to approach a reference time variation.

公开(公告)号：US20210013893A1

公开(公告)日：2021-01-14

申请号：US16923335

申请日：2020-07-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno GAILHARD ,  Laurent TRUPHEMUS ,  Christophe EVA

IPC: H03L7/10 ,  H03L7/099 ,  H03L7/089

Abstract: The operation of the phase-locked loop includes a startup phase where a reference signal having a duty cycle of 50% is applied to a phase comparator of the loop. A first divider of an output signal of the voltage-controlled oscillator of the loop is reset at each first type signal edge of the reference signal. The phase comparator receives the reference signal and a feedback signal from the first divider and generates a control pulse at each second type signal edge of the reference signal that causes a control voltage of the oscillator to increase.

公开(公告)号：US20220158628A1

公开(公告)日：2022-05-19

申请号：US17520063

申请日：2021-11-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno GAILHARD

IPC: H03K3/03 ,  H03K5/00 ,  H03K5/26 ,  H03L7/099 ,  H03L7/093 ,  G06F1/08 ,  G06F1/06

Abstract: A device for generating first clock signals includes first circuits, each including a ring oscillator delivering one of the first clock signals and being connected to a first node configured to receive a first current. A circuit selects one the first clock signals, and a phase-locked loop delivers a second signal which is a function of a difference between a frequency of the first selected clock signal and a set point frequency. Each first circuit supplies the first node with a compensation current determined by the second signal, when this first circuit delivers the selected clock signal and operates in controlled mode.