公开(公告)号：US20170116439A1

公开(公告)日：2017-04-27

申请号：US15137789

申请日：2016-04-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Jimmy Fort ,  Clement Champeix ,  Jean-Max Dutertre ,  Nicolas Borrel

IPC: G06F21/86 ,  H03K5/153 ,  H03K5/24 ,  H01L23/00

CPC classification number: G06F21/86 ,  G09C1/00 ,  H01L23/576 ,  H03K5/153 ,  H03K5/24 ,  H04L9/004 ,  H04L2209/12

Abstract: A secure electronic chip including a plurality of biased semiconductor wells and a well biasing current detection circuit. Each of the wells includes a transistor and a bias contact electrically isolated from the transistor. The detection circuit is electrically coupled to each bias contact and is configured to detect a bias current passing through the bias contact that is indicative of an attempt to tamper with the electronic chip.

公开(公告)号：US10691840B2

公开(公告)日：2020-06-23

申请号：US15137789

申请日：2016-04-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Jimmy Fort ,  Clement Champeix ,  Jean-Max Dutertre ,  Nicolas Borrel

IPC: G06F21/86 ,  G09C1/00 ,  H04L9/00 ,  H01L23/00 ,  H03K5/153 ,  H03K5/24

Abstract: A secure electronic chip including a plurality of biased semiconductor wells and a well biasing current detection circuit. Each of the wells includes a transistor and a bias contact electrically isolated from the transistor. The detection circuit is electrically coupled to each bias contact and is configured to detect a bias current passing through the bias contact that is indicative of an attempt to tamper with the electronic chip.