公开(公告)号：US20240074134A1

公开(公告)日：2024-02-29

申请号：US18230952

申请日：2023-08-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Paul DEVOGE ,  Abderrezak MARZAKI ,  Franck JULIEN ,  Alexandre MALHERBE

IPC: H10B10/00 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B10/12 ,  H01L29/66825 ,  H01L29/788

Abstract: An integrated circuit includes transistor. That transistor is manufactured using a process including the following steps: forming a first gate region; depositing dielectric layers accumulating on sides of the first gate region to form regions of spacers having a width; etching to remove a part of the deposited dielectric layers accumulated on the sides of the first gate region to reduce the width of the regions of spacers; performing a first implantation of dopants aligned on the regions of spacers to form first lightly doped conduction regions of the transistor; and performing a second implanting of dopants to form first more strongly doped conduction regions of the transistor.