THREE-PHASE POWER FACTOR CONTROLLER IMPLEMENTED WITH SINGLE-PHASE POWER FACTOR CORRECTION CONTROLLER

    公开(公告)号:US20230396155A1

    公开(公告)日:2023-12-07

    申请号:US17834174

    申请日:2022-06-07

    CPC classification number: H02M1/4216 H02M1/4225 H02M1/4233 H02M1/12

    Abstract: A PFC correction circuit includes first, second, and third phase inputs coupled to three-phase power mains, with a three-phase full-wave rectifying bridge connected to an input node. First, second, and third boost inductors are respectively connected between first, second, and third phase inputs and first, second, and third taps of the three-phase full-wave rectifying bridge. A boost switch is connected between the input node and ground, and a boost diode is connected between the input node and an output node. A multiplier input driver generates a single-phase input signal as a replica of a signal at the three-phase power mains after rectification. A single-phase power factor controller generates a PWM signal from the single-phase input signal. A gate driver generates a gate drive signal from the PWM signal. The boost switch is operated by the gate drive signal.

    SYSTEM AND METHOD FOR OUTPUT BUS SWITCHING TO ENHANCE EFFICIENCY IN WIDE OUTPUT LLC CONVERTER FOR EV CHARGING

    公开(公告)号:US20220258633A1

    公开(公告)日:2022-08-18

    申请号:US17175143

    申请日:2021-02-12

    Inventor: Ranajay MALLIK

    Abstract: A DC-DC converter includes an inverter converting a DC supply voltage to a time varying signal. A transformer has a primary winding coupled to the inverter through an LC-tank circuit. A diode structure includes a first diode pair coupled in series between a high-voltage bus and a negative output, and a second diode pair coupled in series between the high-voltage bus and the negative output. The transformer has a secondary winding with a first terminal coupled to a tap between the first diode pair and a second terminal coupled to a tap between the second diode pair. A high-voltage bus transistor selectively couples the high-voltage bus to a positive output in response to a high-voltage bus gate drive signal. A low-voltage bus transistor selectively couples a low-voltage bus at a center tap of the secondary winding to the positive output in response to a low-voltage bus gate drive signal.

    QUADRATURE SIGNAL DECODING USING A DRIVER
    4.
    发明申请
    QUADRATURE SIGNAL DECODING USING A DRIVER 审中-公开
    使用驱动程序的正交信号解码

    公开(公告)号:US20140125503A1

    公开(公告)日:2014-05-08

    申请号:US14135156

    申请日:2013-12-19

    CPC classification number: H03M1/303 H03M1/305 H03M1/306 H04L27/22

    Abstract: A system and method for decoding quadrature signals includes a quadrature signal generator, a quadrature signal decoder, a key matrix and a driver. The quadrature signal generator generates quadrature signals on rotation. The quadrature signal decoder is configured to convert the quadrature signals into non-overlapping signals. The key matrix is configured to receive the non-overlapping signals. The driver is configured to scan the key matrix to decode the non-overlapping signals to generate an event update corresponding to a direction of rotation of the quadrature signal generator.

    Abstract translation: 用于解码正交信号的系统和方法包括正交信号发生器,正交信号解码器,密钥矩阵和驱动器。 正交信号发生器在旋转时产生正交信号。 正交信号解码器被配置为将正交信号转换成非重叠信号。 密钥矩阵被配置为接收不重叠的信号。 驱动器被配置为扫描键矩阵以解码不重叠的信号以产生对应于正交信号发生器的旋转方向的事件更新。

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