公开(公告)号：US11476018B2

公开(公告)日：2022-10-18

申请号：US17385625

申请日：2021-07-26

Applicant: STMicroelectronics International N.V.

Inventor： Mohit Kaushik ,  Anil Kumar

IPC: H01C17/26 ,  H01L21/66

Abstract: An amplifier receives an input and a feedback. A first transistor controlled by the amplifier output is coupled between a supply node and the feedback. A second transistor controlled by the amplifier output is coupled to the supply node and generates a bias current. A trimmed resistor coupled between the feedback and ground includes, for trimming resolution of N-bits, where X+Y=N: M resistors, where M=2X−1, each having a resistance equal to R*(2Y)*i, i being an index having a value ranging from 1 to 2X−1, a first of the M resistors having a resistance of R*2Y, a last of the M resistors having a resistance of R*2Y*(2X−1); and M switches associated with the M resistors. Each of the M resistors is between a first node and its associated one of the M switches. Each of the M switches couples its associated one of the M resistors to a second node.

公开(公告)号：US20180337685A1

公开(公告)日：2018-11-22

申请号：US15600152

申请日：2017-05-19

Applicant: STMicroelectronics International N.V.

Inventor： Pratap Narayan Singh ,  Vivek Tripathi ,  Anil Kumar ,  Rakesh Malik

IPC: H03M1/30 ,  H03M1/08 ,  H03M1/06 ,  H03M1/66 ,  H03M1/74

CPC classification number: H03M1/0872 ,  H03M1/0663 ,  H03M1/66 ,  H03M1/742

Abstract: Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.

公开(公告)号：US11107613B2

公开(公告)日：2021-08-31

申请号：US16668023

申请日：2019-10-30

Applicant: STMicroelectronics International N.V.

Inventor： Mohit Kaushik ,  Anil Kumar

IPC: H01C17/26 ,  H01L21/66

Abstract: A resistance trimming circuit has a resolution of N=X+Y bits. Included is a first circuit with M resistors, where M=2X−1, with each of the M resistors having a resistance of R*(2Y)*i, i being an index having a value ranging from 1 to 2X−1. M switches are associated with the M resistors. Each of the M resistors is coupled between a first node and its one of the M switches, and each of the M switches couples its one of the M resistors to a second node. Included is a second circuit with P resistors, where P=2Y−1, with each of the P resistors having a resistance of R*i. P switches are associated with the P resistors. Each of the P resistors is coupled between the second node and its one of the P switches, and each of the P switches selectively couples its one of the P resistors to a third node.

公开(公告)号：US10148277B1

公开(公告)日：2018-12-04

申请号：US15600152

申请日：2017-05-19

Applicant: STMicroelectronics International N.V.

Inventor： Pratap Narayan Singh ,  Vivek Tripathi ,  Anil Kumar ,  Rakesh Malik

IPC: H03M1/08 ,  H03M1/66 ,  H03M1/74 ,  H03M1/06

Abstract: Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.