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公开(公告)号：US11094354B2
公开(公告)日：2021-08-17
申请号：US17015271
申请日：2020-09-09
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Rupesh Singh , Vivek Tripathi
Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.
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Patent Agency Ranking
公开(公告)号：US11451240B2
公开(公告)日：2022-09-20
申请号：US17344450
申请日：2021-06-10
Applicant: STMicroelectronics International N.V.
Inventor： Vivek Tripathi
Abstract: A quad signal generator circuit generates four 2N-1 bit control signals in response to a 2N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N-1 unit DAC elements, with each unit DAC element including four switching circuits controlled by corresponding bits of the four 2N-1 bit control signals. Outputs of the 2N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2N-1 bit thermometer coded signal and a time delay applied to the 2N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N-1 bit thermometer coded signal.
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公开(公告)号：US20180337685A1
公开(公告)日：2018-11-22
申请号：US15600152
申请日：2017-05-19
Applicant: STMicroelectronics International N.V.
Inventor： Pratap Narayan Singh , Vivek Tripathi , Anil Kumar , Rakesh Malik
CPC classification number: H03M1/0872 , H03M1/0663 , H03M1/66 , H03M1/742
Abstract: Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.
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公开(公告)号：US11417371B2
公开(公告)日：2022-08-16
申请号：US17374304
申请日：2021-07-13
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Rupesh Singh , Vivek Tripathi
Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.
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5.发明授权公开(公告)号：US11152951B2
公开(公告)日：2021-10-19
申请号：US17099423
申请日：2020-11-16
Applicant: STMicroelectronics International N.V.
Inventor： Vivek Tripathi
Abstract: A quad signal generator circuit generates four 2N−1 bit control signals in response to a sampling clock and a 2N−1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N−1 unit resistor elements, with each unit resistor element including four switching circuits controlled by corresponding bits of the four 2N−1 bit control signals. Outputs of the 2N−1 unit resistor elements are summed to generate an analog output signal. The quad signal generator circuit controls generation of the four 2N−1 bit control signals such that all logic states of bits of the four 2N−1 bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N−1 bit thermometer coded signal.
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公开(公告)号：US10148277B1
公开(公告)日：2018-12-04
申请号：US15600152
申请日：2017-05-19
Applicant: STMicroelectronics International N.V.
Inventor： Pratap Narayan Singh , Vivek Tripathi , Anil Kumar , Rakesh Malik
Abstract: Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.
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