公开(公告)号：US20240404595A1

公开(公告)日：2024-12-05

申请号：US18676630

申请日：2024-05-29

Applicant: STMicroelectronics International N.V.

Inventor： Antonino CONTE ,  Francesco LA ROSA

IPC: G11C13/00

Abstract: A sense amplifier circuit includes first, second inputs coupled to first, second memory sensing nodes, respectively. A sensing circuit operates to sense a differential signal between the first, second inputs. A first boosting capacitor has a first terminal coupled to the first input and a second terminal coupled to a switchable node. A second boosting capacitor has a first terminal coupled to the second input and a second terminal coupled to the switchable node. Control circuitry operates, responsive to a bitline boost activation signal having a first value, to couple the first terminals of the first, second boosting capacitors to a regulated supply voltage and drive the switchable node to ground. Responsive to the bitline boost activation signal having a second value, the first terminals of the first, second boosting capacitors are decoupled from the regulated supply voltage and the switchable node is driven to the regulated supply voltage.

公开(公告)号：US20240404596A1

公开(公告)日：2024-12-05

申请号：US18676719

申请日：2024-05-29

Applicant: STMicroelectronics International N.V.

Inventor： Antonino CONTE ,  Francesco LA ROSA

IPC: G11C13/00

Abstract: First, second input terminals of a sense amplifier are coupled to first, second memory sensing nodes. A first input transistor has a channel arranged between a first comparator input and a first comparator output, and a control terminal at a bias node. A second input transistor has a channel arranged between a second comparator input and a second comparator output, and a control terminal at a bias node. The first and second comparator inputs are selectively couplable to each other, in response to compensation signal assertion, or to the first and second input terminals, in response to compensation signal de-assertion. The bias node is selectively couplable to a comparator biasing node in response to bias enable assertion, or is floating in response to the bias enable de-assertion. A sensing circuit produces a read signal as a function of a difference between first, second currents at the comparator outputs.

公开(公告)号：US20250095731A1

公开(公告)日：2025-03-20

申请号：US18824446

申请日：2024-09-04

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Antonino CONTE ,  Francesco TOMAIUOLO ,  Jeremie Clement JASSE ,  Anna GANDOLFO

IPC: G11C13/00

Abstract: A method of operating phase change memories and corresponding device and computer program product are provided. An example of write operations in a phase change memory includes: if a first set contains at least one cell set at a high logic level, performing a reset write operation to set to a low logic level the cell by applying at least one current reset pulse; and if a second set contains at least one cell set at a low logic level, performing a set write operation to set to a high logic level the afore the cell. Success or failure of the set write operation is verified. Success or failure of the reset write operation is verified. The write operation is considered as failed in response to the reset write operation being considered as failed or to the set write operation being considered as failed.

公开(公告)号：US20250022509A1

公开(公告)日：2025-01-16

申请号：US18769493

申请日：2024-07-11

Applicant: STMicroelectronics International N.V.

Inventor： Francesco TOMAIUOLO ,  Marco RUTA ,  Michelangelo PISASALE ,  Marion Helne GRIMAL ,  Luigi BUONO ,  Antonino CONTE ,  Diego DE COSTANTINI ,  Marco Eugenio GIBILARO

IPC: G11C13/00

Abstract: A Phase Change Memory (PCM) device includes sets of cells in which a binary logic level is written by a write operation. Each cell is included in a respective set of cells in the sets of cells. The write operation includes: performing write verify operations on the cells to identify an actual logic level stored in the cells; checking if the identified actual logic level matches a certain the binary logic level; in response to the checking determining that in at least one cell the actual logic level fails to match the binary logic level, correcting the actual logic level to match the binary logic level by performing: a set write operation in case the binary logic level is a high logic level, or a reset write operation in case the binary logic level is a low logic level.