公开(公告)号：US11892505B1

公开(公告)日：2024-02-06

申请号：US17945576

申请日：2022-09-15

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Anubhav Arora

IPC: G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/31705 ,  G01R31/31726 ,  G01R31/318597

Abstract: A processing system includes: main and shadow processing cores configured to operate in lockstep based on a core clock. The main processing core includes a main processing core and a main debug circuit. The shadow processing core includes a shadow functional core and a shadow debug circuit. A redundancy checker circuit is configured to assert an alarm signal when a discrepancy between outputs from the main and shadow functional cores is detected. A debug bus synchronizer circuit is configured to receive input debug data in synchrony with a debug clock, and provide synchronized debug data in synchrony with the core clock to a debug bus based on the input debug data, where the main and shadow debug circuits are configured to receive the synchronized debug data in synchrony with the core clock from the debug bus, and where the debug clock is asynchronous with respect to the core clock.