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公开(公告)号：US11892505B1
公开(公告)日：2024-02-06
申请号：US17945576
申请日：2022-09-15
发明人： Avneep Kumar Goyal , Anubhav Arora
IPC分类号： G01R31/317 , G01R31/3185
CPC分类号： G01R31/31705 , G01R31/31726 , G01R31/318597
摘要： A processing system includes: main and shadow processing cores configured to operate in lockstep based on a core clock. The main processing core includes a main processing core and a main debug circuit. The shadow processing core includes a shadow functional core and a shadow debug circuit. A redundancy checker circuit is configured to assert an alarm signal when a discrepancy between outputs from the main and shadow functional cores is detected. A debug bus synchronizer circuit is configured to receive input debug data in synchrony with a debug clock, and provide synchronized debug data in synchrony with the core clock to a debug bus based on the input debug data, where the main and shadow debug circuits are configured to receive the synchronized debug data in synchrony with the core clock from the debug bus, and where the debug clock is asynchronous with respect to the core clock.
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公开(公告)号：US12020760B2
公开(公告)日：2024-06-25
申请号：US18078714
申请日：2022-12-09
CPC分类号： G11C29/38 , G11C7/1084 , G11C7/22 , G11C29/14 , G11C29/36 , G11C2029/1206 , G11C2029/3602 , H03K19/20
摘要： Disclosed herein is a method of operating a system in a test mode. When the test mode is an ATPG test mode, the method includes beginning stuck-at testing by setting a scan control signal to a logic one, setting a transition mode signal to a logic 0, and initializing FIFO buffer for ATPG test mode. The FIFO buffer is initialized for ATPG test mode by setting a scan reset signal to a logic 0 to place a write data register and a read data register associated with the FIFO buffer into a reset state, enabling latches of the FIFO buffer using an external enable signal, removing the external enable signal to cause the latches to latch, and setting the scan reset signal to a logic 1 to release the write data register and the read data register from the reset state, while not clocking the write data register.
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公开(公告)号：US20230133912A1
公开(公告)日：2023-05-04
申请号：US17515212
申请日：2021-10-29
申请人： STMICROELECTRONICS APPLICATION GMBH , STMicroelectronics S.r.l. , STMicroelectronics International N.V.
IPC分类号： G01R31/317 , G01R31/319 , G01R31/28
摘要： A trace-data preparation circuit including a filtering circuit to receive traced memory-write data and a First In First Out buffer coupled with the filtering circuit to receive selected memory-write data filtered by the filtering circuit. The trace-data preparation circuit further including a data compression circuit to provide packaging data to a packaging circuit that groups the selected memory-write data.
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公开(公告)号：US20230281092A1
公开(公告)日：2023-09-07
申请号：US18317420
申请日：2023-05-15
发明人： Avneep Kumar Goyal
IPC分类号： G06F11/263 , G06F1/06 , G06F11/22
CPC分类号： G06F11/263 , G06F1/06 , G06F11/2236
摘要： An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer, and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.
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公开(公告)号：US20230133385A1
公开(公告)日：2023-05-04
申请号：US17515149
申请日：2021-10-29
摘要： A system on a chip including a first-port controller for a first development port configured to receive a first development tool and a second-port controller for a second development port configured to receive a second development tool. The system on a chip further including a central controller in communication with the first-port controller, the second-port controller, and a security subsystem. The central controller being configured to manage authentication exchanges between the security subsystem and the first development tool and authentication exchanges between the security subsystem and the second development tool.
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公开(公告)号：US20210006237A1
公开(公告)日：2021-01-07
申请号：US16460191
申请日：2019-07-02
发明人： Avneep Kumar Goyal
摘要： A synchronizer circuit includes a first synchronizer having a first input for receiving a signal associated with a first clock signal, a second input for receiving a second clock signal, and an output for providing a synchronizer circuit output signal; a second synchronizer having a first input for receiving the signal associated with the first clock signal, a second input for receiving the second clock signal, and an output; a detection stage having a first input coupled to the output of the first synchronizer and to the output of the second synchronizer, a second input for receiving the second clock signal, and an output; and a fault output stage having a first input coupled to the detection stage, a second input for receiving the second clock signal, and an output for providing a fault output signal.
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公开(公告)号：US11914499B2
公开(公告)日：2024-02-27
申请号：US17515212
申请日：2021-10-29
申请人： STMICROELECTRONICS APPLICATION GMBH , STMicroelectronics S.r.l. , STMicroelectronics International N.V.
CPC分类号： G06F11/3636 , G06F11/3082 , G06F11/3466
摘要： A trace-data preparation circuit including a filtering circuit to receive traced memory-write data and a First In First Out buffer coupled with the filtering circuit to receive selected memory-write data filtered by the filtering circuit. The trace-data preparation circuit further including a data compression circuit to provide packaging data to a packaging circuit that groups the selected memory-write data.
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公开(公告)号：US11557364B1
公开(公告)日：2023-01-17
申请号：US17443556
申请日：2021-07-27
摘要： Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.
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公开(公告)号：US10924091B2
公开(公告)日：2021-02-16
申请号：US16460191
申请日：2019-07-02
发明人： Avneep Kumar Goyal
摘要： A synchronizer circuit includes a first synchronizer having a first input for receiving a signal associated with a first clock signal, a second input for receiving a second clock signal, and an output for providing a synchronizer circuit output signal; a second synchronizer having a first input for receiving the signal associated with the first clock signal, a second input for receiving the second clock signal, and an output; a detection stage having a first input coupled to the output of the first synchronizer and to the output of the second synchronizer, a second input for receiving the second clock signal, and an output; and a fault output stage having a first input coupled to the detection stage, a second input for receiving the second clock signal, and an output for providing a fault output signal.
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公开(公告)号：US20240311227A1
公开(公告)日：2024-09-19
申请号：US18122420
申请日：2023-03-16
CPC分类号： G06F11/0793 , G06F1/08 , G06F11/0745
摘要： According to an embodiment, a system is provided that includes a debugging tool and an application board. The debugging tool includes a serial wire debug (SWD) host coupled to a single signal debug port (SSDP) host. The application board includes an SWD target coupled to an SSDP target. The SWD target is configured to communicate SWD signals with the SWD host. The SSDP target is configured to encode the SWD signals to SSDP signals for communication over a Controller Area Network (CAN) Bus between the application board and the debugging tool. The SSDP signals are pulse-width modulation (PWM) encoded signals of the SWD signals. An SWD clock signal generated by the SWD host is the carrier signal for the PWM encoded signals. The SSDP target is configured to decode the SSDP signals received from the SSDP host over the CAN Bus to the SWD signals.
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