公开(公告)号：US20240213101A1

公开(公告)日：2024-06-27

申请号：US18535882

申请日：2023-12-11

Applicant: STMicroelectronics International N.V.

Inventor： Brice ARRAZAT ,  Christian RIVERO

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L27/092

Abstract: An electronic circuit includes a plurality of transistors including: at least one first MOS transistor of a first conductivity type arranged inside and on top of at least one first active area of a semiconductor substrate and at least one second MOS transistor of the second conductivity type arranged inside and on top of at least one second active area of the semiconductor substrate. Each first active area is delimited by a first insulating region which is recessed with respect to a first surface of the semiconductor substrate by a first depth. Each second active area is delimited by a second insulating region which is flush with the first surface of the semiconductor substrate, or which is recessed with respect to the first surface of the semiconductor substrate by a second depth smaller than the first depth.

公开(公告)号：US20240215233A1

公开(公告)日：2024-06-27

申请号：US18540482

申请日：2023-12-14

Applicant: STMicroelectronics International N.V.

Inventor： Brice ARRAZAT ,  Christian RIVERO ,  Julien DELALLEAU ,  Joel METZ

IPC: H10B41/35 ,  H01L21/762 ,  H10B41/10

CPC classification number: H10B41/35 ,  H01L21/76224 ,  H10B41/10

Abstract: An electronic circuit includes a transistor cell with multiple transistors arranged inside and on top of a semiconductor substrate. Each transistor has an active area. First insulating regions are at least partially located around the transistors and extend down to a first depth in the semiconductor substrate. Second insulating regions are positioned to insulate the active areas the transistors from one another. The second insulating regions extend down to a second depth in the semiconductor substrate, the second depth being greater than the first depth.