公开(公告)号：US20220357973A1

公开(公告)日：2022-11-10

申请号：US17736590

申请日：2022-05-04

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMicroelectronics International N.V.

Inventor： Boris VITTORELLI ,  Simrata BATRA ,  Vivek Kumar SOOD ,  Deepak BARANWAL

IPC: G06F9/455

Abstract: A communication system couples a plurality of processing cores together, each having an associated register storing a virtual machine ID, which is inserted into requests sent by the respective processing core. A master circuit has associated a master interface circuit, wherein the master interface circuit has associated register for storing a second virtual machine ID, which is inserted into requests sent by the master circuit. A slave circuit has associated a slave interface circuit configured to selectively forward read or write requests addressed to an address sub-range. The slave interface circuit has associated a third register storing a third virtual machine ID associated with the address sub-range and is configured to receive a request addressed to the address sub-range, extract from the request a virtual machine ID, determine whether the extracted virtual machine ID corresponds to the third virtual machine ID, and then either forwards or rejects the request.

公开(公告)号：US20140047285A1

公开(公告)日：2014-02-13

申请号：US13964299

申请日：2013-08-12

Applicant: STMicroelectronics International N.V.

Inventor： Deepak BARANWAL ,  Digvijay Pratap SINGH ,  Kaushik SAHA

IPC: G11C29/08

CPC classification number: G11C29/08 ,  G11C29/04 ,  G11C29/76 ,  G11C2029/0409

Abstract: An embodiment of a manager includes at least one input node configured to receive information regarding a region of an integrated circuit, and a determiner configured to determine, in response to the information, a likelihood that the region will cause an error. For example, the region may include a memory, and contents of the memory may be transferred to another, more reliable memory, if the likelihood that the memory will cause an error in the data that it stores equals or exceeds a likelihood threshold.

Abstract translation: 管理器的实施例包括被配置为接收关于集成电路的区域的信息的至少一个输入节点，以及被配置为响应于该信息确定该区域将导致错误的可能性的确定器。 例如，如果存储器将导致其存储的数据中的错误等于或超过似然阈值的可能性，则该区域可以包括存储器，并且存储器的内容可以被传送到另一个更可靠的存储器。

公开(公告)号：US20220334862A1

公开(公告)日：2022-10-20

申请号：US17235206

申请日：2021-04-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH

Inventor： Deepak BARANWAL ,  Amritanshu ANAND ,  Roberto COLOMBO ,  Boris VITTORELLI

IPC: G06F9/455 ,  G06F9/30 ,  G06F9/48

Abstract: Disclosed herein is hardware for easing the process of changing the execution mode of a virtual machine and its associated resources. By adopting the hardware, it is possible to trigger a change in the execution mode in an automatic way, without software intervention, and without interfering with the execution of other virtual machines. In addition, in case an error has occurred for a virtual machine and it is detected, the hardware can be used to disable the resources associated with that virtual machine and generate notification of the completion this operation to other hardware, which will complete the reset of the virtual machine. By adopting the hardware, the execution mode change is simplified and offers configurability and flexibility for a system running multiple virtual machines.

公开(公告)号：US20220137128A1

公开(公告)日：2022-05-05

申请号：US17083876

申请日：2020-10-29

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： Avneep Kumar GOYAL ,  Deepak BARANWAL ,  Thomas SZURMANT ,  Nicolas Bernard GROSSIER

IPC: G01R31/317 ,  G01R31/3185

Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.

公开(公告)号：US20210089651A1

公开(公告)日：2021-03-25

申请号：US16579415

申请日：2019-09-23

Applicant: STMicroelectronics International N.V.

Inventor： Deepak BARANWAL ,  Nirav Prashantkumar TRIVEDI ,  Sandip ATAL

IPC: G06F21/55 ,  G06F21/75 ,  G06F9/455 ,  G06F13/16

Abstract: An embedded system includes a peripheral and system-on-a-chip executing virtual machines and a hypervisor. The peripheral includes a crossbar circuit receiving digital sensor signals and selectively outputting the digital sensor signals to different outputs, queue circuits each receiving a different one of the digital sensor signals from the crossbar circuit, and queue protection circuits associated with the queue circuits and selectively permitting access to one of the queue circuits by the virtual machines. The hypervisor controls the queue protection circuits to set which of the virtual machines may access which queue circuits. A sensor protection circuit selectively permits reading of the digital sensor signals from the crossbar circuit by the queue circuits. The hypervisor controls the sensor protection circuit to set which of the queue circuits may access each of the digital sensor signals from the crossbar circuit.