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公开(公告)号：US20220334862A1
公开(公告)日：2022-10-20
申请号：US17235206
申请日：2021-04-20
摘要： Disclosed herein is hardware for easing the process of changing the execution mode of a virtual machine and its associated resources. By adopting the hardware, it is possible to trigger a change in the execution mode in an automatic way, without software intervention, and without interfering with the execution of other virtual machines. In addition, in case an error has occurred for a virtual machine and it is detected, the hardware can be used to disable the resources associated with that virtual machine and generate notification of the completion this operation to other hardware, which will complete the reset of the virtual machine. By adopting the hardware, the execution mode change is simplified and offers configurability and flexibility for a system running multiple virtual machines.
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公开(公告)号：US20230027826A1
公开(公告)日：2023-01-26
申请号：US17858782
申请日：2022-07-06
摘要： A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits. For example the safety monitor circuit comprises a test circuit configured to provide modified data bits and/or modified ECC bits to the error detection circuit as a function of connectivity test control signals, whereby the error detection circuit asserts the error signal as a function of the connectivity test control signals. The processing system comprises also a connectivity test control circuit comprising control registers programmable via the microprocessor, wherein the connectivity test control signals are generated as a function of the content of the control registers.
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3.发明申请公开(公告)号：US20210089329A1
公开(公告)日：2021-03-25
申请号：US17107183
申请日：2020-11-30
摘要： A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.
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公开(公告)号：US20220308645A1
公开(公告)日：2022-09-29
申请号：US17702529
申请日：2022-03-23
IPC分类号： G06F1/24
摘要： A processing system includes a reset circuit, a memory storing configuration data, and a hardware configuration circuit transmitting the configuration data to configuration data clients. The system executes a reset phase, configuration phase, and software runtime phase. First and second reset terminals are associated with first and second circuitries which are respectively associated with configuration data clients. The configuration data includes first and second mode configuration data for the first and second terminals. During the reset and configuration phase, the first circuitry activates a strong pull-down, and the second circuitry activates a weak pull-down. During the software runtime phase, the first circuitry activate a weak pull-down for implementing a bidirectional reset terminal or activates a weak pull-up resistance for implementing a reset output terminal, and the second circuitry activates a weak pull-up for implementing a reset input terminal or activates a strong pull-up for implementing a reset output terminal.
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公开(公告)号：US20220308545A1
公开(公告)日：2022-09-29
申请号：US17704675
申请日：2022-03-25
IPC分类号： G05B19/042
摘要： A set of configuration memory locations store configuration data for a microcontroller unit. A hardware monitoring module is coupled by an interconnection bus to the configuration memory locations. The hardware monitoring module reads from an instruction memory a command including an address of a target memory location in the set of configuration memory locations. Data is read from the target memory location corresponding to the address read and a checksum value is computed as a function of the data that is read from the target memory location. The computed checksum value is then compared to a respective expected checksum value stored in a checksum storage unit. An alarm signal is triggered in response to a mismatch detected between the computed checksum value and the respective expected checksum value.
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6.发明申请公开(公告)号：US20180330123A1
公开(公告)日：2018-11-15
申请号：US15965802
申请日：2018-04-27
CPC分类号： G06F21/71 , G06F11/0721 , G06F11/0751 , G06F11/0772 , G06F21/57 , G06F21/602 , G06F21/77 , H03K19/17728 , H04L9/0618 , H04L2209/12 , H04L2209/127
摘要： A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.
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