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    MULTIPLEXER CIRCUIT USING A TRANSMISSION GATE CIRCUIT WITH A SELECTIVELY BOOSTED SWITCH CONTROL SIGNAL
    1.
    发明申请
    MULTIPLEXER CIRCUIT USING A TRANSMISSION GATE CIRCUIT WITH A SELECTIVELY BOOSTED SWITCH CONTROL SIGNAL 有权

    公开(公告)号：US20220311439A1

    公开(公告)日：2022-09-29

    申请号：US17701870

    申请日：2022-03-23

    Applicant: STMicroelectronics International N.V.

    Inventor： Ramji GUPTA ,  Anand KUMAR

    IPC: H03K17/693 ,  H03K17/687 ,  H03K17/06 ,  H03K19/20

    Abstract: A transmission gate circuit for use, for example, as a switching element of an analog multiplexer, includes an input configured to receive an input signal, an output and a control input configured to receive a switch control signal. A transmission gate switch is coupled between the input and the output. A level shifting circuit generates a level shifted switch control signal from the switch control signal, and applies that level shifted switch control signal to a control terminal of the transmission gate switch. The control terminal of the transmission gate switch can instead receive the switch control signal in situations where a voltage of the input signal is suitably high to support linear operation of the transmission gate switch.

    HIGH PERFORMANCE PHASE LOCKED LOOP FOR MILLIMETER WAVE APPLICATIONS
    2.
    发明申请
    HIGH PERFORMANCE PHASE LOCKED LOOP FOR MILLIMETER WAVE APPLICATIONS 有权

    公开(公告)号：US20220209777A1

    公开(公告)日：2022-06-30

    申请号：US17521210

    申请日：2021-11-08

    Applicant: STMicroelectronics International N.V.

    Inventor： Gagan MIDHA ,  Kallol CHATTERJEE ,  Anand KUMAR ,  Ankit GUPTA

    IPC: H03L7/089 ,  H03L7/197 ,  H03L7/093 ,  H03L7/099

    Abstract: A PLL includes an input comparison circuit comparing a reference signal to a divided feedback signal to thereby control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed, and produces an oscillator control signal causing an oscillator to generate an output signal. Divider circuitry divides the output signal by a divisor to produce the divided feedback signal. Divisor generation circuitry changes the divisor over time so the output signal ramps from a start frequency to an end frequency. Modification circuitry stores a first oscillator control signal equal to the value of the oscillator control signal when the frequency of the output signal is the start ramp frequency. When the frequency of the output signal reaches the end ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.

    LOW POWER CRYSTAL OSCILLATOR WITH AUTOMATIC AMPLITUDE CONTROL
    4.
    发明公开
    LOW POWER CRYSTAL OSCILLATOR WITH AUTOMATIC AMPLITUDE CONTROL 审中-公开

    公开(公告)号：US20230412155A1

    公开(公告)日：2023-12-21

    申请号：US18323998

    申请日：2023-05-25

    Applicant: STMicroelectronics International N.V.

    Inventor： Nitin JAIN ,  Anand KUMAR ,  Kallol CHATTERJEE

    IPC: H03K3/03 ,  H03K3/012 ,  H03K3/354

    CPC classification number: H03K3/0307 ,  H03K3/3545 ,  H03K3/012

    Abstract: A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to further reduce power consumption by the low power crystal oscillator circuit. Additionally, an automatic amplitude detection circuit may turn off the high power part after the amplitude of the crystal oscillation reaches a predetermined level in order to further reduce power consumption of the low power crystal oscillator circuit, and may turn back on the high power part after the amplitude of the crystal oscillation reaches a second predetermined level in order to maintain the crystal oscillation.

    LOW POWER CRYSTAL OSCILLATOR
    6.
    发明申请
    LOW POWER CRYSTAL OSCILLATOR 有权

    公开(公告)号：US20230090782A1

    公开(公告)日：2023-03-23

    申请号：US17931863

    申请日：2022-09-13

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand KUMAR ,  Nitin JAIN

    IPC: H03B5/36

    Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

    PROGRAMMABLE-ON-THE-FLY FRACTIONAL DIVIDER IN ACCORDANCE WITH THIS DISCLOSURE
    7.
    发明申请
    PROGRAMMABLE-ON-THE-FLY FRACTIONAL DIVIDER IN ACCORDANCE WITH THIS DISCLOSURE 有权

    公开(公告)号：US20210281254A1

    公开(公告)日：2021-09-09

    申请号：US17193532

    申请日：2021-03-05

    Applicant: STMicroelectronics International N.V.

    Inventor： Jeet Narayan TIWARI ,  Anand KUMAR ,  Prashutosh GUPTA

    IPC: H03K5/00 ,  H03K19/20

    Abstract: A divider circuit includes a subtract-by-two circuit receiving MSBs of an input and producing a subtracted-by-two output, a subtract-by-one circuit receiving the MSBs and producing a subtracted-by-one output, a first multiplexer passing the subtracted-by-two or the subtracted-by-one output based on a first control signal, a second multiplexer passing output of the first multiplexer or the MSBs based on a second control signal to produce an asynchronous divisor. An asynchronous one-shot N+2 divider divides an input clock by the asynchronous divisor to produce a first divided signal. An output flip-flop receives the first divided signal and is clocked by an inverse of the input clock to produce a second divided signal. A third multiplexer passes the first divided signal or the second divided signal in response to a select load signal to produce a multiplexer output. A divider divides the multiplexer output by a set divisor to produce an output clock.

    LOW NOISE PHASE LOCK LOOP (PLL) CIRCUIT
    8.
    发明公开
    LOW NOISE PHASE LOCK LOOP (PLL) CIRCUIT 审中-公开

    公开(公告)号：US20230163769A1

    公开(公告)日：2023-05-25

    申请号：US17969251

    申请日：2022-10-19

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand KUMAR ,  Prashutosh GUPTA

    IPC: H03L7/197 ,  H03L7/089 ,  H03L7/099 ,  H03L7/093

    CPC classification number: H03L7/1974 ,  H03L7/093 ,  H03L7/0893 ,  H03L7/0995 ,  H03L2207/06

    Abstract: A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.

    ADAPTIVE LOW POWER COMMON MODE BUFFER
    9.
    发明申请
    ADAPTIVE LOW POWER COMMON MODE BUFFER 有权

    公开(公告)号：US20210250036A1

    公开(公告)日：2021-08-12

    申请号：US17245592

    申请日：2021-04-30

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand KUMAR ,  Ramji GUPTA

    IPC: H03M1/12

    Abstract: A circuit includes an amplifier having first and second inputs and an output, and a feedback circuit configured to generate a feedback voltage in response to a voltage at the output of the amplifier. The feedback circuit is coupled to the first input of the amplifier to provide the feedback voltage to the first input of the amplifier. An output circuit is configured to generate a variable bias current in response to the voltage at the output of the amplifier. A switch circuit is configured to switch the second input of the amplifier from receiving a first reference voltage during a first mode of operation to receiving a second reference voltage during a second mode of operation.

    LOCKED LOOP CIRCUIT WITH REFERENCE SIGNAL PROVIDED BY UN-TRIMMED OSCILLATOR
    10.
    发明申请
    LOCKED LOOP CIRCUIT WITH REFERENCE SIGNAL PROVIDED BY UN-TRIMMED OSCILLATOR 审中-公开

    公开(公告)号：US20200076437A1

    公开(公告)日：2020-03-05

    申请号：US16674207

    申请日：2019-11-05

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand KUMAR ,  Nitin GUPTA ,  Nitin JAIN

    IPC: H03L1/00 ,  H03L7/183 ,  H03L7/087

    Abstract: A circuit includes a frequency detector generating a comparison signal as a function of a comparison between a reference signal and a feedback signal. An oscillator generates an output signal as a function of the comparison signal. A frequency divider, in operation, divides the output signal by a division value to produce the feedback signal as having a frequency that is a multiple of a frequency of the reference signal. A frequency counter circuit measures the frequency of the reference signal and generates a count signal based thereupon. A control circuit adjusts the division value used by the frequency divider, in operation, based upon the count signal.

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