公开(公告)号：US10886931B1

公开(公告)日：2021-01-05

申请号：US16937955

申请日：2020-07-24

Applicant: STMicroelectronics International N.V.

Inventor： Rajesh Narwal ,  Kavindu Shekhar Benjwal

IPC: H03M1/00 ,  H03M1/12 ,  H03K3/037 ,  H03K19/20

Abstract: A circuit includes analog input nodes and switches selectively coupling each of the analog input nodes to a capacitive node. Each of the switches is controlled by a respective bit of a channel selection word. Level shifting circuits are respectively coupled in parallel with the switches. A sampling capacitor is coupled between an output node and ground, the output node being coupled to the capacitive node. An analog to digital converter operates to digitize voltages at the output node.

公开(公告)号：US10771082B1

公开(公告)日：2020-09-08

申请号：US16560683

申请日：2019-09-04

Applicant: STMicroelectronics International N.V.

Inventor： Rajesh Narwal ,  Kavindu Shekhar Benjwal

IPC: H03M1/00 ,  H03M1/12 ,  H03K3/037 ,  H03K19/20

Abstract: An analog-to-digital converter includes a sampling capacitor connected to a multiplexer output, discharge circuitry discharging the sampling capacitor during a first period beginning at a start of a sampling cycle, and level shifting circuitry charging the sampling capacitor to a voltage at a first analog input node modified by a mismatch voltage resulting from mismatch in threshold voltages between a first transistor connected to the first analog input node and a second transistor connected to the output node, during a second period beginning at expiration of the first period. A first switch connects the first analog input node to the output node to charge the sampling capacitor to the voltage at the first analog input node, at expiration of the second period, and disconnects the first analog input node from the output node at an end of the sampling cycle of the analog-to-digital converter.