公开(公告)号：US09331671B2

公开(公告)日：2016-05-03

申请号：US14283043

申请日：2014-05-20

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin Gupta ,  Paramjeet Singh Sahni ,  Tapas Nandy ,  Manish Garg

IPC: H04B3/00 ,  H04L25/00 ,  H03K3/01 ,  H04N5/44 ,  H04N5/63 ,  H03K19/0185

CPC classification number: H03K3/01 ,  H03K19/018528 ,  H04N5/44 ,  H04N5/63

Abstract: A power harvesting circuit includes a new transmitter topology that ensures that no junction of thin oxide transistors forming the power harvesting circuit will experience a voltage across junctions of the transistors that is more than a maximum tolerable junction voltage. A supplemental power feed circuit operates to provide a supplemental feed current to components in a transmitter circuit when power harvested from a receiver circuit is insufficient to adequately power these components of the transmitter circuit, which may occur during high frequency operation of communications channels coupling the transmitter and receiver circuits. The supplemental power feed circuit also operates to sink a shunt current when power harvested from the receiver circuit is more than is needed to power the components in the transmitter circuit.

Abstract translation: 功率收集电路包括新的发射机拓扑结构，其确保形成功率收集电路的薄氧化物晶体管的结不会经受超过最大可容忍结电压的晶体管结的电压。 补充供电电路用于在从接收器电路收集的功率不足以对发射机电路的这些组件充分供电时，向发射机电路中的组件提供补充馈电电流，这可能在耦合发射机的通信信道的高频操作期间发生 和接收器电路。 当从接收器电路收集的功率大于为发射机电路中的组件供电所需的功率时，辅助馈电电路还用于吸收分流电流。

公开(公告)号：US11070198B2

公开(公告)日：2021-07-20

申请号：US17005091

申请日：2020-08-27

Applicant: STMicroelectronics International N.V.

Inventor： Manish Garg ,  Ankit Agrawal

IPC: H03K3/0233 ,  H03K3/037 ,  H03K19/20

Abstract: A delay independent differential hysteresis receiver. The differential hysteresis receiver uses two parallel paths in a first receiver stage, each path having a comparator with a dedicated offset on the complimentary inputs. A second receiver stage includes a hold circuit that brings the two parallel paths of the first receiver stage together to form a receiver hysteresis output.

公开(公告)号：US11075624B2

公开(公告)日：2021-07-27

申请号：US16906664

申请日：2020-06-19

Applicant: STMicroelectronics International N.V.

Inventor： Saiyid Mohammad Irshad Rizvi ,  Manish Garg

IPC: H03K19/0185 ,  H03K17/16 ,  H03K19/20 ,  H03K19/0175

Abstract: A hybrid driver receives complementary high-speed input data signals and a pair of low-speed input data signals and selects one of the pairs of input data signals and drives output data signals on first and second output nodes based on the selected pair of input data signals. The hybrid driver includes first and second driver circuits coupled to the first and second output nodes, respectively. Each driver circuit includes first and second series-connected transistors coupled between a first supply voltage node and a reference voltage node, with an interconnection of the first and second series-connected transistors coupled to the corresponding first or second output node. Each first and second driver circuit includes a third transistor coupled in parallel with the corresponding first transistor. Each first and third transistor couples in parallel the corresponding output node to a second supply voltage node responsive to the corresponding low-speed input data signal.