公开(公告)号：US20190312575A1

公开(公告)日：2019-10-10

申请号：US16253410

申请日：2019-01-22

Applicant: STMicroelectronics International N.V.

Inventor： Manoj Kumar Kumar TIWARI ,  Saiyid Mohammad Irshad RIZVI

IPC: H03K17/082 ,  H03K17/687 ,  G05F3/16 ,  H03K19/0185

Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.