公开(公告)号：US20230133385A1

公开(公告)日：2023-05-04

申请号：US17515149

申请日：2021-10-29

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Thomas Szurmant

IPC: G06F21/44 ,  G06F21/31 ,  G06F21/85 ,  G06F11/36

Abstract: A system on a chip including a first-port controller for a first development port configured to receive a first development tool and a second-port controller for a second development port configured to receive a second development tool. The system on a chip further including a central controller in communication with the first-port controller, the second-port controller, and a security subsystem. The central controller being configured to manage authentication exchanges between the security subsystem and the first development tool and authentication exchanges between the security subsystem and the second development tool.

公开(公告)号：US20230133912A1

公开(公告)日：2023-05-04

申请号：US17515212

申请日：2021-10-29

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Thomas Szurmant ,  Misaele Marletti ,  Alessandro Daolio

IPC: G01R31/317 ,  G01R31/319 ,  G01R31/28

Abstract: A trace-data preparation circuit including a filtering circuit to receive traced memory-write data and a First In First Out buffer coupled with the filtering circuit to receive selected memory-write data filtered by the filtering circuit. The trace-data preparation circuit further including a data compression circuit to provide packaging data to a packaging circuit that groups the selected memory-write data.

公开(公告)号：US20250036518A1

公开(公告)日：2025-01-30

申请号：US18911745

申请日：2024-10-10

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Thomas Szurmant

IPC: G06F11/07 ,  G06F1/08

Abstract: According to an embodiment, a system is provided that includes a debugging tool and an application board. The debugging tool includes a serial wire debug (SWD) host coupled to a single signal debug port (SSDP) host. The application board includes an SWD target coupled to an SSDP target. The SWD target is configured to communicate SWD signals with the SWD host. The SSDP target is configured to encode the SWD signals to SSDP signals for communication over a Controller Area Network (CAN) Bus between the application board and the debugging tool. The SSDP signals are pulse-width modulation (PWM) encoded signals of the SWD signals. An SWD clock signal generated by the SWD host is the carrier signal for the PWM encoded signals. The SSDP target is configured to decode the SSDP signals received from the SSDP host over the CAN Bus to the SWD signals.

公开(公告)号：US11914499B2

公开(公告)日：2024-02-27

申请号：US17515212

申请日：2021-10-29

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Thomas Szurmant ,  Misaele Marletti ,  Alessandro Daolio

IPC: G06F11/36 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F11/3636 ,  G06F11/3082 ,  G06F11/3466

Abstract: A trace-data preparation circuit including a filtering circuit to receive traced memory-write data and a First In First Out buffer coupled with the filtering circuit to receive selected memory-write data filtered by the filtering circuit. The trace-data preparation circuit further including a data compression circuit to provide packaging data to a packaging circuit that groups the selected memory-write data.

公开(公告)号：US12210609B2

公开(公告)日：2025-01-28

申请号：US17515149

申请日：2021-10-29

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Thomas Szurmant

IPC: G06F21/85 ,  G06F11/362 ,  G06F21/31 ,  G06F21/44 ,  G06F21/45 ,  G06F21/71

Abstract: A system on a chip including a first-port controller for a first development port configured to receive a first development tool and a second-port controller for a second development port configured to receive a second development tool. The system on a chip further including a central controller in communication with the first-port controller, the second-port controller, and a security subsystem. The central controller being configured to manage authentication exchanges between the security subsystem and the first development tool and authentication exchanges between the security subsystem and the second development tool.

公开(公告)号：US20240311227A1

公开(公告)日：2024-09-19

申请号：US18122420

申请日：2023-03-16

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Thomas Szurmant

IPC: G06F11/07 ,  G06F1/08

CPC classification number: G06F11/0793 ,  G06F1/08 ,  G06F11/0745

Abstract: According to an embodiment, a system is provided that includes a debugging tool and an application board. The debugging tool includes a serial wire debug (SWD) host coupled to a single signal debug port (SSDP) host. The application board includes an SWD target coupled to an SSDP target. The SWD target is configured to communicate SWD signals with the SWD host. The SSDP target is configured to encode the SWD signals to SSDP signals for communication over a Controller Area Network (CAN) Bus between the application board and the debugging tool. The SSDP signals are pulse-width modulation (PWM) encoded signals of the SWD signals. An SWD clock signal generated by the SWD host is the carrier signal for the PWM encoded signals. The SSDP target is configured to decode the SSDP signals received from the SSDP host over the CAN Bus to the SWD signals.

公开(公告)号：US11360143B2

公开(公告)日：2022-06-14

申请号：US17083876

申请日：2020-10-29

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： Avneep Kumar Goyal ,  Deepak Baranwal ,  Thomas Szurmant ,  Nicolas Bernard Grossier

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3193 ,  G06F11/34 ,  G01R31/319 ,  G06F11/36

Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.