公开(公告)号：US20240290364A1

公开(公告)日：2024-08-29

申请号：US18441110

申请日：2024-02-14

Applicant: STMicroelectronics International N.V.

Inventor： Leonardo VALENCIA RISSETTO ,  Alin RAZAFINDRAIBE ,  Xavier LECOQ ,  Christophe FOREL

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1063 ,  G11C7/1066

Abstract: A device includes memory cells wherein each memory cell has a control input that receives a pulse-width modulated control voltage and an output that delivers a current depending on the control voltage and on a weight programmed in the memory cell. A node receives, during a first time period, the currents of the memory cells. A first circuit delivers an output determined by a total quantity of current received by the node during the first time period. For each memory cell, a second circuit receives a digital word and delivers, during the first time period, the pulse-width modulated control voltage at a first level only during a second time period determined by the digital word.

公开(公告)号：US20250104747A1

公开(公告)日：2025-03-27

申请号：US18886002

申请日：2024-09-16

Applicant: STMicroelectronics International N.V.

Inventor： Alin RAZAFINDRAIBE ,  Thomas JOUANNEAU ,  Xavier LECOQ

IPC: G11C7/10 ,  G11C11/54

Abstract: A non-volatile memory includes a first area with first storage elements configured to store values associated with first neurons of a network and a second area with second storage elements. A control circuit applies one or more first input values to first read paths, each first read path including one among the first storage elements. A computing circuit adds currents supplied by the first read paths to generate an output current. A programming circuit converts the output current into a programming current, and uses the programming current to program a second storage element.

公开(公告)号：US20240386955A1

公开(公告)日：2024-11-21

申请号：US18660938

申请日：2024-05-10

Applicant: STMicroelectronics International N.V.

Inventor： Xavier LECOQ ,  Alin RAZAFINDRAIBE ,  Christophe FOREL

IPC: G11C13/00

Abstract: A phase-change memory cell to be read is associated with a phase-change reference memory cell placed in a SET state. The reference memory cell has a structure that is identical to that of the memory cell. A first voltage is applied to the memory cell to cause output of a first current. A second voltage is applied to the reference memory cell to cause output of a second current. A sense amplifier is coupled to the memory cell and to the reference memory cell and is configured to compare respective values of the first current and of the second current and generate output information representative of the logic value of the datum stored by the memory cell.

公开(公告)号：US20240386954A1

公开(公告)日：2024-11-21

申请号：US18660651

申请日：2024-05-10

Applicant: STMicroelectronics International N.V.

Inventor： Xavier LECOQ ,  Alin RAZAFINDRAIBE

IPC: G11C13/00

Abstract: A multi-level non-volatile memory cell has N levels, N being even and greater than two, corresponding respectively to N logical data that can be stored in the memory cell and to N corresponding read current ranges. A datum stored in the memory cell is read by performing successive comparisons of a read current output by the memory cell with reference currents selected from a set of N-1 reference currents having values respectively lying between two different successive ranges using a dichotomous algorithm starting with the reference current having the median value.