公开(公告)号：US10418987B2

公开(公告)日：2019-09-17

申请号：US16052449

申请日：2018-08-01

Applicant: STMicroelectronics KK

Inventor： Luca Bartolomeo ,  Kazuo Eguchi ,  Giuseppe Davide Bruno

IPC: H03L5/00 ,  H03K19/0185 ,  H03K17/16 ,  H01L29/16 ,  H03K17/10 ,  H03K3/313 ,  H03K17/691 ,  H01L29/78

Abstract: A level shifting circuit has an input configured to receive an input signal, wherein the input signal has symmetrical maximum and minimum voltages. The level shifting circuit further includes an output configured to provide an output signal, wherein the output signal has asymmetrical maximum and minimum voltages. The output signal is generated in response to the input signal. The output signal is applied to drive a gate terminal of a SiC MOSFET.

公开(公告)号：US20180191341A1

公开(公告)日：2018-07-05

申请号：US15396964

申请日：2017-01-03

Applicant: STMicroelectronics KK

Inventor： Luca Bartolomeo ,  Kazuo Eguchi ,  Giuseppe Davide Bruno

IPC: H03K17/16 ,  H01L29/16 ,  H01L29/78 ,  H03K17/10 ,  H03K3/313

CPC classification number: H03K17/161 ,  H01L29/1608 ,  H01L29/78 ,  H03K3/313 ,  H03K17/102 ,  H03K17/162 ,  H03K17/691 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: A level shifting circuit has an input configured to receive an input signal, wherein the input signal has symmetrical maximum and minimum voltages. The level shifting circuit further includes an output configured to provide an output signal, wherein the output signal has asymmetrical maximum and minimum voltages. The output signal is generated in response to the input signal. The output signal is applied to drive a gate terminal of a SiC MOSFET.

公开(公告)号：US10063227B2

公开(公告)日：2018-08-28

申请号：US15396964

申请日：2017-01-03

Applicant: STMicroelectronics KK

Inventor： Luca Bartolomeo ,  Kazuo Eguchi ,  Giuseppe Davide Bruno

IPC: H03L5/00 ,  H03K19/0185 ,  H03K17/16 ,  H01L29/16 ,  H01L29/78 ,  H03K17/10 ,  H03K3/313

Abstract: A level shifting circuit has an input configured to receive an input signal, wherein the input signal has symmetrical maximum and minimum voltages. The level shifting circuit further includes an output configured to provide an output signal, wherein the output signal has asymmetrical maximum and minimum voltages. The output signal is generated in response to the input signal. The output signal is applied to drive a gate terminal of a SiC MOSFET.

公开(公告)号：US20180343005A1

公开(公告)日：2018-11-29

申请号：US16052449

申请日：2018-08-01

Applicant: STMicroelectronics KK

Inventor： Luca Bartolomeo ,  Kazuo Eguchi ,  Giuseppe Davide Bruno

IPC: H03K17/16 ,  H01L29/16 ,  H03K17/10 ,  H03K3/313 ,  H01L29/78

CPC classification number: H03K17/161 ,  H01L29/1608 ,  H01L29/78 ,  H03K3/313 ,  H03K17/102 ,  H03K17/162 ,  H03K17/691 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: A level shifting circuit has an input configured to receive an input signal, wherein the input signal has symmetrical maximum and minimum voltages. The level shifting circuit further includes an output configured to provide an output signal, wherein the output signal has asymmetrical maximum and minimum voltages. The output signal is generated in response to the input signal. The output signal is applied to drive a gate terminal of a SiC MOSFET.