公开(公告)号：US20020175703A1

公开(公告)日：2002-11-28

申请号：US10145390

申请日：2002-05-14

Applicant: STMicroelectronics Ltd.

Inventor： Ankur Bal

IPC: H03K019/173

CPC classification number: H03K19/17728

Abstract: A look-up table circuit includes address decoder circuitry that includes circuitry for utilizing the address decoder circuitry for producing secondary functions concurrently with operation of the address decoding operations. This eliminates or reduces secondary functions.

Abstract translation: 查找表电路包括地址解码器电路，其包括用于利用地址解码器电路与地址解码操作的操作同时产生辅助功能的电路。 这消除或减少了次要功能。

公开(公告)号：US20020194449A1

公开(公告)日：2002-12-19

申请号：US10172355

申请日：2002-06-14

Applicant: STMicroelectronics Ltd.

Inventor： Ankur Bal

IPC: G06F009/34

CPC classification number: H03K19/17728

Abstract: A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is provided. The system may include a single set of storage elements connected to the inputs of multiple decoders, and the storage elements may be concurrently accessed by the decoders to provide simultaneous multiple outputs thereto.

Abstract translation: 提供了一种用于减少实现布尔函数所需的查找表中可编程体系结构元素数量或相同或逻辑等价的操作的系统。 该系统可以包括连接到多个解码器的输入的单组存储元件，并且存储元件可以由解码器同时访问以向其提供同时多个输出。

公开(公告)号：US20030005402A1

公开(公告)日：2003-01-02

申请号：US10186314

申请日：2002-06-28

Applicant: STMicroelectronics Ltd.

Inventor： Ankur Bal

IPC: G06F017/50

CPC classification number: H03K19/1776 ,  H03K19/17736 ,  H03K19/17744

Abstract: A system for simplifying the programmable memory-to-logic interface in field programmable gate arrays (FPGAs) is provided. An interface may be used to isolate the general purpose routing architecture for intra-programmable logic blocks (PLBs) from the random access memory (RAM) address lines, data lines, and control lines. The PLBs and the input-output resources of the FPGA access the embedded memory (or RAM) using dedicated direct interconnects. Certain of these direct interconnects may originate from PLBs in the vicinity of the RAM. The remainder run between the input-output (IO) pads/routing and the RAM blocks. A bus routing architecture is also provided to combine the memories to emulate larger RAM blocks. This bus routing provides interconnection among RAM blocks and is isolated from the PLB routing resources.

Abstract translation: 提供了一种用于简化现场可编程门阵列（FPGA）中的可编程存储器到逻辑接口的系统。 可以使用接口来隔离来自随机存取存储器（RAM）地址线，数据线和控制线的可编程逻辑块（PLB）的通用路由架构。 FPGA的PLB和输入输出资源使用专用直接互连访问嵌入式存储器（或RAM）。 这些直接互连中的某些可能来自RAM附近的PLB。 剩余部分在输入 - 输出（IO）焊盘/路由和RAM块之间运行。 还提供总线路由架构以组合存储器以模拟较大的RAM块。 该总线路由提供RAM块之间的互连，并与PLB路由资源隔离。

公开(公告)号：US20020114200A1

公开(公告)日：2002-08-22

申请号：US10072458

申请日：2002-02-07

Applicant: STMicroelectronics Ltd.

Inventor： Ankur Bal

IPC: G11C007/00

CPC classification number: H03K19/17776

Abstract: A system for relatively rapidly configuring reconfigurable devices with a plurality of latches is provided. The number of clock cycles for loading the configuration data may be reduced by a substantial amount, and the fidelity of data loaded into the configuration latches may be relatively high. The invention also incorporates procedures for configuring multiple reconfigurable devices, which are similar to daisy chaining techniques.

Abstract translation: 提供了一种用于相对快速地配置具有多个锁存器的可重新配置设备的系统。 用于加载配置数据的时钟周期的数量可以减少大量，并且加载到配置锁存器中的数据的保真度可能相对较高。 本发明还包括用于配置多个可重新配置设备的过程，其类似于菊花链技术。

公开(公告)号：US20020113618A1

公开(公告)日：2002-08-22

申请号：US10072461

申请日：2002-02-07

Applicant: STMicroelectronics Ltd.

Inventor： Ankur Bal

IPC: H03K019/173

CPC classification number: H03K19/17748 ,  H03K19/17728 ,  H03K19/17736

Abstract: A programmable logic device may include a programmable interconnect structure and a plurality of configurable logic elements including data latches interconnected by the interconnect structure. At least one of the configurable logic elements may be configurable as both a shift register and a lookup table. Also, the shift register may be enabled to operate as a bi-directional shift register by the inclusion of a first circuit for configuring the data latches either as series-connected inverters during a shift operation or as data latches after each shift operation. A second circuit for selecting a direction of shifting may also be included, as well as a third circuit for supplying data to the input of the shift register as determined by the direction of shifting.

Abstract translation: 可编程逻辑器件可以包括可编程互连结构以及包括通过互连结构互连的数据锁存器的多个可配置逻辑元件。 可配置逻辑元件中的至少一个可以被配置为移位寄存器和查找表。 此外，移位寄存器可以通过在移位操作期间包括用于配置数据锁存器作为串联连接的反相器的第一电路或者在每个移位操作之后的数据锁存器中而被允许作为双向移位寄存器操作。 还可以包括用于选择移位方向的第二电路，以及用于向由移位方向确定的移位寄存器的输入端提供数据的第三电路。