公开(公告)号：US20020048201A1

公开(公告)日：2002-04-25

申请号：US09948146

申请日：2001-09-06

Applicant: STMicroelectronics Ltd.

Inventor： Anurag Garg

IPC: G11C029/00

CPC classification number: G11C11/412 ,  G11C8/16

Abstract: A first-in, first-out (FIFO) memory cell architecture is provided in which one node of the latch in the FIFO memory cell is connected to the gate of the pass transistor. Further, the bit line is connected to the source of the pass transistor, and the word line is connected to the drain of the pass transistor to provide a stable memory cell requiring less area for implementation.

Abstract translation: 提供先入先出（FIFO）存储单元结构，其中FIFO存储单元中的锁存器的一个节点连接到传输晶体管的栅极。 此外，位线连接到传输晶体管的源极，并且字线连接到传输晶体管的漏极，以提供一个稳定的存储单元，其需要较少的实现面积。

公开(公告)号：US20020091894A1

公开(公告)日：2002-07-11

申请号：US09917226

申请日：2001-07-27

Applicant: STMicroelectronics Ltd.

Inventor： Anurag Garg

IPC: G06F012/00 ,  G06F012/14 ,  G06F012/16 ,  G06F013/00 ,  G06F013/28

CPC classification number: G11C17/16 ,  G06F2213/0038 ,  G11C11/5692

Abstract: A high bit density, high speed, via and metal BE type programmable ROM core cell architecture for storing large amounts of non-volatile data and having a relatively fast turn around time is provided. The ROM core cell may include memory cells organized in rows and columns where each of the memory cells includes three transistors and two bit lines. The arrangement between the three transistors and two bit lines may be such that each of the memory cells is capable of storing four bits of data.

Abstract translation: 提供了用于存储大量非易失性数据并且具有相对较快的周转时间的高比特密度，高速度，通孔和金属BE型可编程ROM核心单元架构。 ROM核心单元可以包括以行和列组织的存储单元，其中每个存储单元包括三个晶体管和两个位线。 三个晶体管和两个位线之间的布置可以使得每个存储器单元能够存储四位数据。