公开(公告)号：US20030086518A1

公开(公告)日：2003-05-08

申请号：US10285329

申请日：2002-10-30

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Kalyana Chakravarthy

IPC: H04L007/02 ,  H03D003/24

CPC classification number: H04N21/4305 ,  H03L7/0992 ,  H03L7/181

Abstract: A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source means includes of a controllable digital fractional divider means receiving a control value from digital comparator means and a clock input from a digital clock synthesizer means driven by a fixed oscillator means.

Abstract translation: 一种用于从包含嵌入式参考时钟值的数据流中恢复时钟的方法和改进装置，所述控制时钟源装置包括从数字比较器装置接收控制值的可控数字分数器装置和由数字比较器装置驱动的数字时钟合成器装置的时钟输入 固定振荡器装置。

公开(公告)号：US20030076137A1

公开(公告)日：2003-04-24

申请号：US10269838

申请日：2002-10-10

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Kalyana Chakravarthy

IPC: H03K023/50

CPC classification number: H03L7/1976 ,  H03K23/68

Abstract: An improved fractional divider that comprises an integer value storage means containing the integer part of the division value nullKnull connected to the input of a programmable counter means that is configured for a count value of nullKnull or nullKnull1null depending upon the state of a count control signal and generates the output signal as well a terminal count signal which is connected to an enable input of a fractional accumulator means that produces the count control signal on an addition overflow and has a first input connected to its result output and a second input connected to the output of a fractional value storage means, containing the fractional part of the divider value.

Abstract translation: 一种改进的分数分割器，其包括整数值存储装置，其包含连接到可编程计数器装置的输入的除法值“K”的整数部分，该可编程计数器装置被配置用于计数值“K”或“K + 1”，这取决于 计数控制信号的状态，并且产生输出信号以及终端计数信号，该终端计数信号连接到分数累加器装置的使能输入，该分数累加器装置在加法溢出时产生计数控制信号，并且具有连接到其结果输出的第一输入 以及连接到分数值存储装置的输出的第二输入，其包含分频值的小数部分。