公开(公告)号：US20030234667A1

公开(公告)日：2003-12-25

申请号：US10460040

申请日：2003-06-10

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Kailash Digari ,  Nitin Deshmukh

IPC: G06F007/38

CPC classification number: H03K19/17772 ,  H03K19/1737 ,  H03K19/17728

Abstract: The present invention provides a Programmable Logic Device (PLD) incorporating a two-input multiplexer for providing a Cascade Logic output and having a Cascade Logic input coupled to a select line. A two-input multiplexer provides the desired configurable Cascade Logic function, and an initialization circuit sets the initial value for the Cascade logic under control of an initialization configuration bit. The multiplexer that provides the Cascade Logic output also provides the desired configurable Cascade Logic function using the Look-up table (LUT) and configuration bits.

Abstract translation: 本发明提供了一种结合了双输入多路复用器的可编程逻辑器件（PLD），用于提供级联逻辑输出并具有耦合到选择线的级联逻辑输入。 双输入多路复用器提供所需的可配置级联逻辑功能，初始化电路在初始化配置位的控制下设置级联逻辑的初始值。 提供级联逻辑输出的多路复用器还使用查找表（LUT）和配置位提供所需的可配置级联逻辑功能。