HIGH JITTER AND FREQUENCY DRIFT TOLERANT CLOCK DATA RECOVERY
    1.
    发明申请
    HIGH JITTER AND FREQUENCY DRIFT TOLERANT CLOCK DATA RECOVERY 有权
    高抖动和频率干扰容忍时钟数据恢复

    公开(公告)号:US20130181754A1

    公开(公告)日:2013-07-18

    申请号:US13784571

    申请日:2013-03-04

    Inventor: Nitin GUPTA

    CPC classification number: H03L7/199 H03L7/0807 H03L7/0812 H03L7/091 H04L7/0337

    Abstract: In a method for recovery of a dock from a received digital data stream and an apparatus for recovering a clock from a received digital data stream, phase-shifted dock signals are generated from a receiver's dock. After selecting one of the phase-shifted clock signals, two other phase-shifted clock signals are determined. Depending on sample values taken at rising/falling edges of the three selected phase-shifted clock signals, counter values are increased and compared. The selection of phase-shifted clock signals and the steps of sampling the input digital data stream, comparing the values and increasing counter values, if required, are repeatedly performed until the comparison result of the counter values indicates that one of the latter determined phase-shifted clock signals strobes the received digital data stream in the centre of a bit period.

    Abstract translation: 在从接收到的数字数据流中恢复基座的方法以及从接收的数字数据流中恢复时钟的装置中,从接收器的基座产生相移的停靠信号。 在选择一个相移时钟信号之后,确定另外两个相移时钟信号。 根据在三个选定的相移时钟信号的上升沿/下降沿采集的采样值,增加和比较计数器值。 如果需要,相移时钟信号的选择和对输入数字数据流进行采样的步骤,比较值和增加计数器值,直到计数器值的比较结果指示后一个确定的相位时钟信号之一, 移位的时钟信号在接收到的位数周期的中心选通接收到的数字数据流。

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