公开(公告)号：US20020135379A1

公开(公告)日：2002-09-26

申请号：US10060105

申请日：2002-01-29

Applicant: STMicroelectronics S.A.

Inventor： Christophe Moreaux ,  Ahmed Kari

IPC: G01R031/00

CPC classification number: G01R31/043

Abstract: A device for detecting a defective power supply connection in an integrated circuit includes a comparison circuit for comparing voltage levels of an input/output pad of the integrated circuit and an internal power supply line connected to a power supply pad of the integrated circuit. A pull-down or pull-up device is connected between the input/output pad and the internal power supply line.

Abstract translation: 用于检测集成电路中的有缺陷的电源连接的装置包括比较电路，用于比较集成电路的输入/输出焊盘的电压电平和连接到集成电路的电源焊盘的内部电源线。 在输入/输出板和内部电源线之间连接一个下拉或上拉设备。

公开(公告)号：US20020180487A1

公开(公告)日：2002-12-05

申请号：US10115869

申请日：2002-04-03

Applicant: STMicroelectronics S.A.

Inventor： Ahmed Kari ,  Christophe Moreaux

IPC: H03K019/00

CPC classification number: G06K7/10346 ,  G06K7/10019 ,  G06K19/0723 ,  G07C9/00111

Abstract: An integrated circuit having an identification code of M bits includes a communication interface circuit for receiving a selective identification request and a selection code, and a processing circuit connected thereto. The processing circuit includes a logic comparator having a first input for receiving the selection code and a second input for receiving the identification code, and an output for delivering an equal signal if the selection and identification codes are equal. A shift register has an output coupled to the first input of the logic comparator. A serial memory stores the identification code, and has a serial output coupled to the second input of the logic comparator and to a serial input of the shift register. A controller is connected to the shift register and to the serial memory for loading the selection code into the shift register, and for applying M shift pulses to the shift register and M read pulses to the serial memory. An inhibiting circuit inhibits the logic comparator when N shift and read pulses have been applied to the shift register and to the serial memory.

Abstract translation: 具有M位识别码的集成电路包括用于接收选择性识别请求和选择码的通信接口电路以及与其连接的处理电路。 处理电路包括具有用于接收选择码的第一输入和用于接收识别码的第二输入的逻辑比较器，以及如果选择和识别码相等则输出相等信号的输出。 移位寄存器具有耦合到逻辑比较器的第一输入的输出。 串行存储器存储识别码，并且具有耦合到逻辑比较器的第二输入端的串行输出和移位寄存器的串行输入。 控制器连接到移位寄存器和串行存储器，用于将选择代码加载到移位寄存器中，并且将M移位脉冲施加到移位寄存器，并将M个读取脉冲施加到串行存储器。 当N移位和读取脉冲已经被施加到移位寄存器和串行存储器时，抑制电路禁止逻辑比较器。

公开(公告)号：US20020079949A1

公开(公告)日：2002-06-27

申请号：US10085845

申请日：2002-02-26

Applicant: STMicroelectronics S.A.

Inventor： Christophe Moreaux

IPC: H01H037/76

CPC classification number: H01L27/118 ,  H03K19/1731 ,  H03K19/1736

Abstract: A configurable electronic circuit having configuration nodes is provided. Each of the configuration nodes is coupled to corresponding first circuitry that is non-modifiable during configuration and second circuitry that is modifiable during the configuration. The non-modifiable first circuitry selectively imposes one of at least a first potential and a second potential on the configuration node prior to configuration, and the modifiable second circuitry allows modification of the potential imposed on the configuration node by the non-modifiable first circuitry. In a preferred embodiment, the modifiable second circuitry includes at least one fuse that is in an intact state before configuration and that can be changed to a destroyed state after configuration. This enables a reduction in the number of fuses that have to be destroyed during the configuration of the circuit. Also provided is an information processing system that includes at least one configurable electronic circuit having configuration nodes.