Reduced-size integrated phase-locked loop
    1.
    发明申请
    Reduced-size integrated phase-locked loop 有权
    减小尺寸的集成锁相环

    公开(公告)号:US20040212410A1

    公开(公告)日:2004-10-28

    申请号:US10776931

    申请日:2004-02-11

    CPC classification number: H03L7/18 H03L7/0891 H03L7/0996

    Abstract: A phase-locked loop comprising a comparator generating a control voltage depending on the phase-shift between a reference signal and a feedback signal, an oscillator controlled by the control voltage, generating several phase-shifted signals of same period, one of which forms the output signal of the phase-locked loop, a multiplexer capable of providing any of the phase-shifted signals to the input of a divider, the output of which forms the feedback signal, and a means controlling the multiplexer to successively provide fractions of the phase-shifted signals, so that the divider receives a signal having an average period equal to a real fraction of the period of the phase-shifted signals.

    Abstract translation: 一种锁相环,包括比较器,其产生取决于参考信号和反馈信号之间的相移的控制电压,由控制电压控制的振荡器,产生相同周期的多个相移信号,其中之一形成 输出信号的多路复用器,能够将任何相移信号提供给分频器的输入,分频器的输出形成反馈信号,以及控制多路复用器的装置,以连续地提供相位的分数 转换信号,使得分频器接收具有等于相移信号的周期的实际分数的平均周期的信号。

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