公开(公告)号：US20020146042A1

公开(公告)日：2002-10-10

申请号：US10039765

申请日：2001-11-07

Applicant: STMicroelectronics S.A.

Inventor： Franck Roche ,  Pierre Tarayre

IPC: H04J003/06

CPC classification number: G06F13/4286

Abstract: The method is for transmitting data between two devices via a clock wire or line and at least one data wire or line. The clock wire is maintained by default on a logic value A, and each device is capable of tying the clock wire to an electric potential representing a logic value B that is the opposite of A. According to the method, both devices tie the clock wire to B when a datum is transmitted, the device to which the datum is sent does not release the clock wire while it has not read the datum, and the device sending the datum maintains the datum on the data wire at least until an instant when the clock wire is released by the device to which the datum is sent. The method is particularly applicable to communication between a microcomputer and a microprocessor.

Abstract translation: 该方法用于经由时钟线或线路和至少一条数据线或线路在两个设备之间传输数据。 时钟线在默认情况下保持在逻辑值A上，并且每个器件能够将时钟线绑定到表示与A相反的逻辑值B的电位。根据该方法，两个器件将时钟线 到B时，发送数据时，发送数据的设备在没有读取数据的情况下不会释放时钟线，并且发送数据的设备至少在数据线上维护数据，直到当时 时钟线由发送基准的设备释放。 该方法特别适用于微型计算机与微处理器之间的通信。