公开(公告)号：US20040221141A1

公开(公告)日：2004-11-04

申请号：US10779855

申请日：2004-02-17

Applicant: STMicroelectronics S.A.

Inventor： Gosagan Padmanabhan ,  Dragos Davidescu ,  Franck Roche

IPC: G06F009/30

CPC classification number: G06F9/30123 ,  G06F9/3004 ,  G06F9/4486 ,  G06F9/461

Abstract: The present invention relates to a method for managing the stack of a microprocessor comprising a central processing unit and a memory array, the central processing unit comprising registers containing contextual data and a stack pointer, the stack being a zone of the memory array used for saving contextual data upon a switch from a first to a second program. According to the present invention, the method comprises saving contextual data contained in a variable number of registers that varies according to the value of at least one flag stored in a register to be saved. Advantages: optimization of the filling of the stack and of the number of subprograms that can be interleaved.

Abstract translation: 本发明涉及一种用于管理包括中央处理单元和存储器阵列的微处理器的堆叠的方法，所述中央处理单元包括包含上下文数据的寄存器和堆栈指针，所述堆栈是用于保存的存储器阵列的区域 从第一程序切换到第二程序时的上下文数据。 根据本发明，该方法包括保存包含在根据存储在要保存的寄存器中的至少一个标志的值而变化的可变数目的寄存器中的上下文数据。 优点：优化堆栈的填充以及可以交错的子程序数量。

公开(公告)号：US20020156818A1

公开(公告)日：2002-10-24

申请号：US10068568

申请日：2002-02-06

Applicant: STMicroelectronics S.A.

Inventor： Franck Roche ,  Nicolas Lafargue

IPC: G06F007/00

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F7/575 ,  G06F7/768 ,  G06F9/30025 ,  G06F9/30032

Abstract: A microprocessor comprises a central processing unit having an arithmetic and logic unit with two inputs and one input fed-back to one of the inputs through a data path. The arithmetic and logic unit performs arithmetic and logic operations on binary words temporarily stored within registers in the central processing unit. The central processing unit further includes a shift unit in the data path of the arithmetic and logic unit for performing operations to shift bits in the binary words applied thereto. A selection circuit selects a shift operation to be performed. An inverting circuit inverts the ordering of the bits in the binary words applied thereto, which are in the data path of the arithmetic and logic unit, and a selection circuit selects the inversion operation when the latter is required.

Abstract translation: 微处理器包括中央处理单元，其具有具有两个输入的算术和逻辑单元，以及通过数据路径反馈到其中一个输入的一个输入。 算术和逻辑单元对临时存储在中央处理单元中的寄存器内的二进制字执行算术和逻辑运算。 中央处理单元还包括在算术和逻辑单元的数据路径中的移位单元，用于执行将应用于其中的二进制字中的位移位的操作。 选择电路选择要执行的移位操作。 反相电路将应用于其中的二进制字中的位的顺序反转在算术和逻辑单元的数据路径中，并且当需要后者时，选择电路选择反转操作。

公开(公告)号：US20040174945A1

公开(公告)日：2004-09-09

申请号：US10758680

申请日：2004-01-15

Applicant: STMicroelectronics S.A.

Inventor： Sandrine Lendre ,  Franck Roche ,  Olivier Plourde

IPC: H03K025/00

CPC classification number: G06F1/04

Abstract: The present invention relates to an integrated circuit comprising a first clock circuit delivering a first clock signal, a second clock circuit delivering a second clock signal, a first counting circuit for delivering a time base signal using a clock signal and a counting value, and means for applying the first clock signal and a first counting value to the first counting circuit, so as to produce a first time base signal. According to the present invention, the integrated circuit comprises means for producing a second time base signal using the second clock signal and a second counting value, and means for calibrating the second counting value such that it is equal or proportional to the number of periods of the second clock signal occurring during a determined time interval equal to a period or to a whole number of periods of the first time base signal. Application particularly to the management of a timer in a microprocessor.

Abstract translation: 本发明涉及一种集成电路，其包括：传送第一时钟信号的第一时钟电路，传递第二时钟信号的第二时钟电路，用于使用时钟信号和计数值传送时基信号的第一计数电路;以及装置 用于将第一时钟信号和第一计数值应用于第一计数电路，以产生第一时基信号。 根据本发明，集成电路包括用于使用第二时钟信号和第二计数值产生第二时基信号的装置，以及用于校准第二计数值的装置，使得其等于或等于 所述第二时钟信号在等于所述第一时基信号的周期或整数个周期的确定时间间隔内发生。 尤其适用于微处理器中定时器的管理。

公开(公告)号：US20030088749A1

公开(公告)日：2003-05-08

申请号：US10273417

申请日：2002-10-17

Applicant: STMicroelectronics S.A.

Inventor： Franck Roche ,  Andre Colomb

IPC: G06F012/00

CPC classification number: G06F9/30032 ,  G06F9/30181

Abstract: A microprocessor includes internal registers, an arithmetic and logic unit, and reads a program memory and executes an instruction set stored therein. The instruction set includes at least one instruction for exchanging the contents of both memory locations. The microprocessor includes an additional internal register connected to an output of the arithmetic and logic unit, and transfers the contents of a first one of the memory locations to be exchanged into the additional register when executing the instruction set. The microprocessor further transfers the contents of a second one of the memory locations to be exchanged into the first memory location, and transfers the contents of the additional register into the first memory location.

Abstract translation: 微处理器包括内部寄存器，算术和逻辑单元，并读取程序存储器并执行存储在其中的指令集。 指令集包括用于交换两个存储器位置的内容的至少一个指令。 微处理器包括连接到算术和逻辑单元的输出的附加内部寄存器，并且在执行指令集时将要交换的存储单元的第一个存储单元的内容传送到附加寄存器中。 微处理器进一步将待交换的存储器位置的第二个的内容传送到第一存储器位置，并将附加寄存器的内容传送到第一存储器位置。

公开(公告)号：US20020146042A1

公开(公告)日：2002-10-10

申请号：US10039765

申请日：2001-11-07

Applicant: STMicroelectronics S.A.

Inventor： Franck Roche ,  Pierre Tarayre

IPC: H04J003/06

CPC classification number: G06F13/4286

Abstract: The method is for transmitting data between two devices via a clock wire or line and at least one data wire or line. The clock wire is maintained by default on a logic value A, and each device is capable of tying the clock wire to an electric potential representing a logic value B that is the opposite of A. According to the method, both devices tie the clock wire to B when a datum is transmitted, the device to which the datum is sent does not release the clock wire while it has not read the datum, and the device sending the datum maintains the datum on the data wire at least until an instant when the clock wire is released by the device to which the datum is sent. The method is particularly applicable to communication between a microcomputer and a microprocessor.

Abstract translation: 该方法用于经由时钟线或线路和至少一条数据线或线路在两个设备之间传输数据。 时钟线在默认情况下保持在逻辑值A上，并且每个器件能够将时钟线绑定到表示与A相反的逻辑值B的电位。根据该方法，两个器件将时钟线 到B时，发送数据时，发送数据的设备在没有读取数据的情况下不会释放时钟线，并且发送数据的设备至少在数据线上维护数据，直到当时 时钟线由发送基准的设备释放。 该方法特别适用于微型计算机与微处理器之间的通信。

公开(公告)号：US20020129234A1

公开(公告)日：2002-09-12

申请号：US09995251

申请日：2001-11-27

Applicant: STMicroelectronics S.A.

Inventor： Franck Roche ,  Pascal Narche ,  Ludovic Ruat

IPC: G06F009/00

CPC classification number: G06F11/2273 ,  G01R31/31701 ,  G01R31/31719

Abstract: A microprocessor includes a counter having a counting input and a reset input. The counting input is coupled to a first terminal of the microprocessor for the selection of an operating mode thereof by application of a predetermined number of pulses to the first terminal. The reset input of the counter is driven by a control signal present on a second terminal of the microprocessor. The control signal is maintained by default at a first logic value ensuring the maintaining at zero of the counter during the initialization period by a circuit internal or external the microprocessor. Immunity against electromagnetic perturbations causing the microprocessor to enter into the test mode is provided.

Abstract translation: 微处理器包括具有计数输入和复位输入的计数器。 计数输入耦合到微处理器的第一端，用于通过向第一终端施加预定数量的脉冲来选择其操作模式。 计数器的复位输入由存在于微处理器的第二端子上的控制信号驱动。 控制信号默认维持在第一逻辑值，确保在初始化期间通过内部或外部微处理器的电路将计数器保持在零。 提供了防止导致微处理器进入测试模式的电磁扰动的抗扰度。

公开(公告)号：US20020113535A1

公开(公告)日：2002-08-22

申请号：US09997195

申请日：2001-11-28

Applicant: STMicroelectronics S.A.

Inventor： Franck Roche ,  Thierry Bouquier

IPC: H01J027/00

CPC classification number: G06F11/2236

Abstract: A microprocessor may be switchable between a normal mode and a test mode for performing a test program and may include a central processing unit (CPU) for saving contextual data in a stack of the microprocessor at the time of switching to the test mode. The CPU may deliver, at the beginning of the test program and on an input/output port, contextual data present in the stack beginning with the top of the stack. The CPU may also decrement a stack pointer by a value corresponding to a number of contextual data delivered.

Abstract translation: 微处理器可以在正常模式和用于执行测试程序的测试模式之间切换，并且可以包括用于在切换到测试模式时将上下文数据保存在微处理器的堆栈中的中央处理单元（CPU）。 CPU可以在测试程序开始时和在输入/输出端口上递送以堆栈顶部开头的堆栈中存在的上下文数据。 CPU也可以将堆栈指针减少与传递的上下文数据的数量相对应的值。