公开(公告)号：US20020020872A1

公开(公告)日：2002-02-21

申请号：US09976484

申请日：2001-10-12

Applicant: STMicroelectronics S.r.I.

Inventor： Carlo Cremonesi ,  Bruno Vajana ,  Roberta Bottini ,  Giovanna Dalla Libera

IPC: H01L029/788 ,  H01L029/76 ,  H01L029/792

CPC classification number: H01L27/11521 ,  H01L21/2652 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825

Abstract: A process formes a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer depositing and partly defining a first polysilicon layer forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor depositing a second polysilicon layer selectively etching away the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor and selectively etching away the interpoly dielectric layer and the first polysilicon layer at the cell. After forming and before partially defining the first polysilicon layer, the process implants at least at the channel region of the floating-gate storage transistor for adjusting the transistor threshold.

Abstract translation: 一种工艺形成了结合有至少一个电路晶体管和EEPROM型的至少一个非易失性存储单元的结构，其中两个自对准多晶硅层具有存储晶体管和相关选择晶体管，该半导体材料包括场氧化物区域 边界活跃区域。 该方法包括以下步骤：在有源区域中，形成栅极氧化物层并限定栅极氧化物层中包括的隧道氧化物区域，沉积并部分地限定形成多晶硅互连层的第一多晶硅层，并至少除去多晶硅绝缘层 在电路晶体管处沉积第二多晶硅层选择性地蚀刻掉电池处的第二多晶硅层，以及在电路晶体管处的第一和第二多晶硅层，并且选择性地蚀刻离开电池的多晶硅间介电层和第一多晶硅层。 在形成之后并且在部分地限定第一多晶硅层之前，该工艺至少在浮栅存储晶体管的沟道区域处注入以调整晶体管阈值。

公开(公告)号：US20020063268A1

公开(公告)日：2002-05-30

申请号：US10056564

申请日：2001-10-26

Applicant: STMicroelectronics S.r.I.

Inventor： Bruno Vajana ,  Matteo Patelmo

IPC: H01L021/82 ,  H01L027/10

CPC classification number: H01L27/11226 ,  H01L23/573 ,  H01L27/02 ,  H01L27/112 ,  Y10S257/922

Abstract: A read only memory (ROM) device includes a semiconductor substrate having a first type of conductivity, and a plurality of memory cells on the semiconductor substrate. Each memory cell includes first and second regions of a second conductivity type opposite the first conductivity type. A first dielectric layer is on the plurality of memory cells, and a plurality of first contacts extend through the first dielectric layer for contacting the first regions. A second dielectric layer is on the first dielectric layer and the plurality of first contacts. A plurality of second contacts extend through the second dielectric layer and overlie the corresponding second regions. The plurality of second contacts define interconnection contacts by further extending through the first dielectric layer for contacting the second regions for memory cells programmed in a conductive state, and false interconnection contacts by not extending through the first dielectric layer for contacting the second regions for memory cells programmed in a non-conductive state.

Abstract translation: 只读存储器（ROM）器件包括具有第一类型导电性的半导体衬底和半导体衬底上的多个存储单元。 每个存储单元包括与第一导电类型相反的第二导电类型的第一和第二区域。 第一介电层位于多个存储单元上，并且多个第一触点延伸穿过第一介电层以接触第一区域。 第二电介质层位于第一电介质层和多个第一接触件上。 多个第二触点延伸穿过第二介电层并且覆盖相应的第二区域。 多个第二触点通过进一步延伸穿过第一介电层来限定互连触点，以接触用于以导电状态编程的存储器单元的第二区域，以及通过不延伸穿过第一介电层以接触存储器单元的第二区域的假互连触点 编程在非导通状态。