Cycle-by-cycle reverse current limiting in ACF converters

    公开(公告)号:US11699956B2

    公开(公告)日:2023-07-11

    申请号:US17989877

    申请日:2022-11-18

    CPC classification number: H02M3/33569 H02M1/08

    Abstract: In an embodiment, a method for operating an ACF converter includes: turning on a low-side transistor that is coupled between a primary winding of a transformer and a reference terminal to cause a forward current to enter the primary winding, turning off the low-side transistor; after turning off the low-side transistor, turning on a high-side transistor that is coupled between the primary winding and a clamp capacitor to cause a reverse current to flow through the primary winding; and after turning on the high-side transistor, when an overcurrent of the reverse current is not detected, keeping the high-side transistor on for a first period of time, and turning off the high-side transistor after the first period of time, and when the overcurrent of the reverse current is detected, turning off the high-side transistor without keeping the high-side transistor on for the first period of time.

    CYCLE-BY-CYCLE REVERSE CURRENT LIMITING IN ACF CONVERTERS

    公开(公告)号:US20230141001A1

    公开(公告)日:2023-05-11

    申请号:US17989877

    申请日:2022-11-18

    CPC classification number: H02M3/33569 H02M1/08

    Abstract: In an embodiment, a method for operating an ACF converter includes: turning on a low-side transistor that is coupled between a primary winding of a transformer and a reference terminal to cause a forward current to enter the primary winding, turning off the low-side transistor; after turning off the low-side transistor, turning on a high-side transistor that is coupled between the primary winding and a clamp capacitor to cause a reverse current to flow through the primary winding; and after turning on the high-side transistor, when an overcurrent of the reverse current is not detected, keeping the high-side transistor on for a first period of time, and turning off the high-side transistor after the first period of time, and when the overcurrent of the reverse current is detected, turning off the high-side transistor without keeping the high-side transistor on for the first period of time.

    SYNCHRONOUS RECTIFIER CONTROL CIRCUIT AND METHOD

    公开(公告)号:US20230143391A1

    公开(公告)日:2023-05-11

    申请号:US17523561

    申请日:2021-11-10

    Inventor: Claudio Adragna

    CPC classification number: H02M3/33592 H02M1/08

    Abstract: In an embodiment, a method for controlling a synchronous rectifier (SR) transistor of a flyback converter includes: determining a first voltage across conduction terminals of the SR transistor; asserting a turn-on signal when a body diode of the SR transistor is conducting current; asserting a turn-off signal when current flowing through the conduction terminals of the SR transistor decreases below a first threshold; generating a gating signal based on an output voltage of the flyback converter and on the first voltage; turning on the SR transistor based on the turn-on signal and on the gating signal; and turning off the SR transistor based on the turn-off signal.

    Burst-mode control method for low input power consumption in resonant converters and related control device
    4.
    发明授权
    Burst-mode control method for low input power consumption in resonant converters and related control device 有权
    谐振变换器及相关控制装置低输入功耗的突发模式控制方法

    公开(公告)号:US09160236B2

    公开(公告)日:2015-10-13

    申请号:US13931564

    申请日:2013-06-28

    Abstract: An effective method enhances energy saving at low load in a resonant converter with a hysteretic control scheme for implementing burst-mode at light load. The method causes a current controlled oscillator of the converter to stop oscillating when a feedback control current of the output voltage of the converter reaches a first threshold value, and introduces a nonlinearity in the functional relation between the frequency of oscillation and said feedback control current or in a derivative of the functional relation, while the control current is between a lower, second threshold value and the first threshold value, such that the frequency of oscillation remains equal or smaller than the frequency of oscillation when the control current is equal to the second threshold value. Several circuital implementations are illustrated, all of simple realization without requiring any costly microcontroller.

    Abstract translation: 一种有效的方法,在谐振转换器中,在负载较小的情况下,能够提供低负荷的节能,并采用迟滞控制方案,以实现轻载时的突发模式。 当转换器的输出电压的反馈控制电流达到第一阈值时,该方法使转换器的电流控制振荡器停止振荡,并且在振荡频率和所述反馈控制电流之间的功能关系中引入非线性,或 在所述功能关系的导数中,当所述控制电流在第二阈值和所述第一阈值之间时,使得当所述控制电流等于所述第二阈值时,所述振荡频率保持等于或小于所述振荡频率 阈值。 示出了几种电路实现,所有这些都是简单的实现,而不需要任何昂贵的微控制器。

    INTEGRATED CIRCUIT FOR CONTROLLING A SWITCH OF A CURRENT PATH WITH LEADING EDGE BLANKING DEVICE OF THE CURRENT SIGNAL
    5.
    发明申请
    INTEGRATED CIRCUIT FOR CONTROLLING A SWITCH OF A CURRENT PATH WITH LEADING EDGE BLANKING DEVICE OF THE CURRENT SIGNAL 有权
    用于控制电流信号开关的集成电路与电流信号的边沿封装装置

    公开(公告)号:US20130057323A1

    公开(公告)日:2013-03-07

    申请号:US13666853

    申请日:2012-11-01

    CPC classification number: H02M3/33507 H02M3/33515 H02M3/33553

    Abstract: An integrated control circuit of a switch is described, which is adapted to open or close a current path; said integrated circuit includes a comparator to compare a first signal with a second signal representative of the current flowing through said current path. The comparator outputs a third variable signal between a low logic level and a high logic level according to whether said second signal is lower than said first signal or vice versa; the integrated circuit has a driver to generate a signal to drive said switch in response to the third signal, and is configured to detect a spike on the leading edge of said second signal and to blank said third signal for a first blanking time period which depends on a turn-on delay of said switch and a second blanking period which depends on the duration of said spike on the leading edge of said second signal.

    Abstract translation: 描述了开关的集成控制电路,其适于打开或关闭电流路径; 所述集成电路包括比较器,用于将第一信号与表示流过所述电流路径的电流的第二信号进行比较。 所述比较器根据所述第二信号是否低于所述第一信号而输出低逻辑电平和高逻辑电平之间的第三可变信号,反之亦然; 所述集成电路具有驱动器,以产生响应于所述第三信号来驱动所述开关的信号,并且被配置为检测所述第二信号的前沿上的尖峰,并且将所述第三信号置为空白,所述第一消隐时间段取决于 在所述开关的导通延迟上,以及取决于所述第二信号的前沿上的所述尖峰的持续时间的第二消隐周期。

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