公开(公告)号：US20020163848A1

公开(公告)日：2002-11-07

申请号：US10124494

申请日：2002-04-17

Applicant: STMicroelectronics S.r.I.

Inventor： Giuseppe GRASSO

IPC: G11C008/00

CPC classification number: G11C11/40615 ,  G11C7/1018 ,  G11C7/1045 ,  G11C11/406

Abstract: A random access memory (RAM) includes at least two memory banks. Each memory bank includes an array of dynamic random access memory (DRAM) cells, and self-refresh circuits for continuously submitting the DRAM cells to a refresh operation independent of the other memory banks. A first circuit selectively accesses one of the memory banks in response to an external access request. A second circuit suspends the refresh operation in the accessed memory bank while processing the external access request, and while the refresh operations in non-selected memory banks are not suspended.

Abstract translation: 随机存取存储器（RAM）包括至少两个存储体。 每个存储体包括动态随机存取存储器（DRAM）单元阵列和用于连续地将DRAM单元提交到独立于其它存储体的刷新操作的自刷新电路。 第一电路响应于外部访问请求选择性地访问存储体之一。 第二电路在处理外部访问请求时以及在未选择的存储体中的刷新操作不被暂停的情况下暂停在所访问的存储体中的刷新操作。