公开(公告)号：US11996158B2

公开(公告)日：2024-05-28

申请号：US18349565

申请日：2023-07-10

Applicant: STMicroelectronics S.r.I.

Inventor： Giampiero Borgonovo ,  Lorenzo Re Fiorentin

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/4401

Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.

公开(公告)号：US20240095057A1

公开(公告)日：2024-03-21

申请号：US18457229

申请日：2023-08-28

Applicant: STMicroelectronics S.r.I.

Inventor： Giampiero Borgonovo ,  Lorenzo Re Fiorentin

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45583 ,  G06F2009/45595

Abstract: A system, for use in providing media access control (MAC)/router/switch/gateway features in an on-board communication network in a vehicle, includes MAC controllers configured to provide a MAC port layer controlling exchange of information over a data link, virtual machine (VM) bridge blocks configured to provide a MAC frame layer interfacing with System-on-Chip VMs, a software (SW) Ethernet port configured to receive from a host programming/configuration information for the system, a local memory controller configured to facilitate the MAC controllers, the VM bridge blocks and the SW Ethernet port in cooperating with a local memory (LMEM), and queue handlers configured to provide queue management for the MAC controllers, the VM bridge blocks and the SW Ethernet port, during cooperation with the LMEM via the local memory controller.

公开(公告)号：US20230360716A1

公开(公告)日：2023-11-09

申请号：US18349565

申请日：2023-07-10

Applicant: STMicroelectronics S.r.I.

Inventor： Giampiero Borgonovo ,  Lorenzo Re Fiorentin

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/4401

Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.