公开(公告)号：US20040029307A1

公开(公告)日：2004-02-12

申请号：US10428338

申请日：2003-05-01

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Ciovacco ,  Simone Alba ,  Roberto Colombo ,  Chiara Savardi

IPC: H01L021/00

CPC classification number: H01L21/823437 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76804 ,  H01L21/76816

Abstract: A method for manufacturing semiconductor-integrated electronic circuits comprises: depositing an auxiliary layer on a substrate; depositing a layer of screening material on the auxiliary layer; selectively removing the layer of screening material to provide a first opening in the layer of screening material and expose an area of the auxiliary layer; and removing this area of the auxiliary layer to form a second opening in the auxiliary layer, whose cross-section narrows toward the substrate to expose an area of the substrate being smaller than the area exposed by the first opening.

Abstract translation: 一种用于制造半导体集成电子电路的方法包括：在衬底上沉积辅助层; 在辅助层上沉积一层筛选材料; 选择性地去除所述筛选材料层以在所述筛选材料层中提供第一开口并暴露所述辅助层的区域; 并且去除辅助层的该区域以在辅助层中形成第二开口，其横截面朝向衬底变窄，以暴露衬底的区域小于由第一开口暴露的区域。