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公开(公告)号:US20220271663A1
公开(公告)日:2022-08-25
申请号:US17650463
申请日:2022-02-09
Applicant: STMicroelectronics S.r.I. , STMicroelectronics (Alps) SAS
Inventor: Francois Druilhe , Patrik Arno , Alessandro Inglese , Michele Alessandro Carrano
Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.
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公开(公告)号:US10965212B2
公开(公告)日:2021-03-30
申请号:US16385214
申请日:2019-04-16
Applicant: STMicroelectronics (Alps) SAS
Inventor: Patrik Arno
IPC: H02M3/156
Abstract: In an embodiment, an SMPS comprises a half-bridge, and a driver configured to drive the half-bridge based on a PWM signal. The SMPS further comprising a first circuit coupled between the output of the driver and a control terminal of a high-side transistor of the half-bridge, wherein the first circuit is configured to maintain the first transistor on when the PWM signal has a duty cycle that is substantially 100%.
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公开(公告)号:US20210203226A1
公开(公告)日:2021-07-01
申请号:US17200498
申请日:2021-03-12
Applicant: STMicroelectronics (Alps) SAS
Inventor: Patrik Arno
IPC: H02M3/156
Abstract: In an embodiment, an SMPS comprises a half-bridge, and a driver configured to drive the half-bridge based on a PWM signal. The SMPS further comprising a first circuit coupled between the output of the driver and a control terminal of a high-side transistor of the half-bridge, wherein the first circuit is configured to maintain the first transistor on when the PWM signal has a duty cycle that is substantially 100%.
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公开(公告)号:US11283353B2
公开(公告)日:2022-03-22
申请号:US16385284
申请日:2019-04-16
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Inventor: Francois Druilhe , Patrik Arno , Alessandro Inglese , Michele Alessandro Carrano
Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.
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公开(公告)号:US20190319540A1
公开(公告)日:2019-10-17
申请号:US16385214
申请日:2019-04-16
Applicant: STMicroelectronics (Alps) SAS
Inventor: Patrik Arno
IPC: H02M3/158
Abstract: In an embodiment, an SMPS comprises a half-bridge, and a driver configured to drive the half-bridge based on a PWM signal. The SMPS further comprising a first circuit coupled between the output of the driver and a control terminal of a high-side transistor of the half-bridge, wherein the first circuit is configured to maintain the first transistor on when the PWM signal has a duty cycle that is substantially 100%.
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公开(公告)号:US10014834B1
公开(公告)日:2018-07-03
申请号:US15393550
申请日:2016-12-29
Applicant: STMicroelectronics (Alps) SAS
Inventor: Vratislav Michal , Denis Cottin , Patrik Arno , Nicolas Marty
Abstract: An embodiment circuit includes a first voltage divider coupled between a first voltage level and a ground potential. The circuit further includes an error amplifier having a first input terminal coupled to a node between a first resistive element and a second resistive element of the first voltage divider. The circuit further includes a second voltage divider coupled between a second voltage level and a reference voltage, wherein a second input terminal of the error amplifier is coupled to a node between a third resistive element and a fourth resistive element of the second voltage divider, and wherein an output voltage of the error amplifier is configured to control a potential difference between the first voltage level and the second voltage level.
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公开(公告)号:US10803911B2
公开(公告)日:2020-10-13
申请号:US15884229
申请日:2018-01-30
Applicant: STMICROELECTRONICS (ALPS) SAS
Inventor: Patrik Arno
Abstract: A current sense amplifier includes: first and second intermediate nodes coupled to first and second nodes of a sense resistor by a chopper, and to respective branches of a current mirror; a differential amplifier having inputs coupled to the first and second intermediate nodes and adapted to generate first and second voltage signals; and first and second transistors adapted to be controlled by the first and second voltage signals respectively and each having one of its main current conducting nodes coupled to a respective one of the first and second intermediate nodes.
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公开(公告)号:US20180301174A1
公开(公告)日:2018-10-18
申请号:US15884229
申请日:2018-01-30
Applicant: STMICROELECTRONICS (ALPS) SAS
Inventor: Patrik Arno
CPC classification number: G11C7/062 , G01R15/14 , G01R19/0092 , G06F1/189 , G06F13/4282 , G11C7/08
Abstract: A current sense amplifier includes: first and second intermediate nodes coupled to first and second nodes of a sense resistor by a chopper, and to respective branches of a current mirror; a differential amplifier having inputs coupled to the first and second intermediate nodes and adapted to generate first and second voltage signals; and first and second transistors adapted to be controlled by the first and second voltage signals respectively and each having one of its main current conducting nodes coupled to a respective one of the first and second intermediate nodes.
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公开(公告)号:US20180191317A1
公开(公告)日:2018-07-05
申请号:US15393550
申请日:2016-12-29
Applicant: STMicroelectronics (Alps) SAS
Inventor: Vratislav Michal , Denis Cottin , Patrik Arno , Nicolas Marty
IPC: H03F3/45
CPC classification number: H03F3/45071 , H03F1/3211 , H03F3/45 , H03F3/45085 , H03F2200/471 , H03F2203/45544 , H03F2203/45594
Abstract: An embodiment circuit includes a first voltage divider coupled between a first voltage level and a ground potential. The circuit further includes an error amplifier having a first input terminal coupled to a node between a first resistive element and a second resistive element of the first voltage divider. The circuit further includes a second voltage divider coupled between a second voltage level and a reference voltage, wherein a second input terminal of the error amplifier is coupled to a node between a third resistive element and a fourth resistive element of the second voltage divider, and wherein an output voltage of the error amplifier is configured to control a potential difference between the first voltage level and the second voltage level.
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公开(公告)号:US20170351286A1
公开(公告)日:2017-12-07
申请号:US15364454
申请日:2016-11-30
Applicant: STMicroelectronics (Alps) SAS
Inventor: Patrik Arno
IPC: G05F1/625
Abstract: A device for controlling a first voltage with a second voltage includes a first terminal of application of the second voltage and a second terminal for supplying the first voltage. A comparator has a first input terminal connected to the first terminal and has a second input terminal receiving information representative of the first voltage. At least one first current source of programmable intensity is connected to the second input terminal of the comparator.
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