公开(公告)号：US20020158285A1

公开(公告)日：2002-10-31

申请号：US10165010

申请日：2002-06-06

Applicant: STMicroelectronics S.r.l.

Inventor： Cesare Clementi ,  Gabriella Ghidini ,  Mauro Alessandri

IPC: H01L029/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825

Abstract: A process of fabricating a floating-gate memory device, the process including the steps of: forming a stack of superimposed layers including a floating gate region, a dielectric region, and a control gate region; and forming an insulating layer of oxynitride to the side of the floating gate region to completely seal the floating gate region outwards and improve the retention characteristics of the memory device. The insulating layer is formed during reoxidation of the sides of the floating gate region, after self-align etching the stack of layers and implanting the source/drain of the cell.