公开(公告)号：US20040203250A1

公开(公告)日：2004-10-14

申请号：US10746878

申请日：2003-12-23

Applicant: STMicroelectronics S.r.l.

Inventor： Cesare Clementi ,  Alessia Pavan ,  Livio Baldi

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A semiconductor substrate has active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed on the substrate and a first layer of conductive material is then deposited. Non-volatile memory cells are manufactured thereon by defining floating gate regions. The definition of these floating gate regions involves defining the first layer of conductive material in order to form a plurality of alternated stripes above pairs of active areas alternated by active areas lacking stripes. Spacers are then formed in the shelter of the side walls of the alternated stripes. A second layer of conductive material is then deposited together with the first layer of conductive material. The spacers are then selectively removed.

Abstract translation: 半导体衬底具有由绝缘层的部分限定的有源区域。 在衬底上形成隧道氧化物薄层，然后沉积第一层导电材料。 通过限定浮动栅极区域在其上制造非易失性存储器单元。 这些浮动栅极区域的定义涉及限定第一层导电材料，以便形成由有缺陷条纹的有源区域交替的一对有源区域之上的多个交替条纹。 然后在交替条纹的侧壁的遮蔽物中形成间隔物。 然后第二层导电材料与第一层导电材料一起沉积。 然后选择性地去除间隔物。

公开(公告)号：US20030111689A1

公开(公告)日：2003-06-19

申请号：US10274314

申请日：2002-10-17

Applicant: STMicroelectronics S.r.l.

Inventor： Maurizio Moroni ,  Cesare Clementi

IPC: H01L021/44 ,  H01L029/76 ,  H01L029/94 ,  H01L031/062

CPC classification number: H01L29/6659 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66659

Abstract: Process for forming salicide on active areas of MOS transistors, each MOS transistor comprising a gate and respective source and drain regions, the source and drain regions each comprising a first lightly doped sub-region adjacent the gate and a second highly doped sub-region spaced apart from the gate. The salicide is formed selectively at least over the second highly doped sub-regions of the source and drain regions of the MOS transistors, and not over the first lightly doped sub-region.

公开(公告)号：US20020158285A1

公开(公告)日：2002-10-31

申请号：US10165010

申请日：2002-06-06

Applicant: STMicroelectronics S.r.l.

Inventor： Cesare Clementi ,  Gabriella Ghidini ,  Mauro Alessandri

IPC: H01L029/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825

Abstract: A process of fabricating a floating-gate memory device, the process including the steps of: forming a stack of superimposed layers including a floating gate region, a dielectric region, and a control gate region; and forming an insulating layer of oxynitride to the side of the floating gate region to completely seal the floating gate region outwards and improve the retention characteristics of the memory device. The insulating layer is formed during reoxidation of the sides of the floating gate region, after self-align etching the stack of layers and implanting the source/drain of the cell.

公开(公告)号：US20040209472A1

公开(公告)日：2004-10-21

申请号：US10749020

申请日：2003-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Cesare Clementi ,  Alessia Pavan ,  Livio Baldi

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method is described for manufacturing non-volatile memory cells on a semiconductive substrate having active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed and a first layer of conductive material is then deposited. A plurality of floating gate regions are defined by forming stripes of shielding material only above pairs of alternated active areas. Spacers of a selective material are defined with respect to the shielding material and of small width at will in the shelter of the side walls of the stripes thus defined. A shielding material is also deposited on the active areas which lacked it. The formation of the floating gate is completed by leaving the definition of the distance between the floating gate regions to the spacers.

Abstract translation: 描述了一种用于在具有由绝缘层的部分界定的有源区域的半导体衬底上制造非易失性存储器单元的方法。 形成隧道氧化物的薄层，然后沉积第一层导电材料。 通过仅在交替的有效区域对之上形成屏蔽材料条来限定多个浮动栅极区域。 选择性材料的间隔相对于屏蔽材料限定，并且在如此限定的条纹的侧壁的遮蔽物中随意地被限定。 屏蔽材料也沉积在缺乏它的有源区上。 通过将浮动栅极区域之间的距离定义为间隔物来完成浮栅的形成。