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公开(公告)号：US10812090B2
公开(公告)日：2020-10-20
申请号：US16681469
申请日：2019-11-12
Applicant: STMicroelectronics S.r.l.
Inventor： Giorgio Mussi , Giacomo Langfelder , Carlo Valzasina , Gabriele Gattere
Abstract: In an embodiment, a clock generator has a variable-modulus frequency divider that receives a high-frequency clock signal and outputs a divided clock signal having a frequency controlled by a modulus-control signal generated by a temperature-compensation circuit. A jitter filter is coupled to the output of the variable-modulus frequency divider and to the temperature-compensation circuit and generates a compensated clock signal having switching edges that are delayed, with respect to the divided clock signal, by a time correlated to a quantization-error signal.
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公开(公告)号：US20200169262A1
公开(公告)日：2020-05-28
申请号：US16681469
申请日：2019-11-12
Applicant: STMicroelectronics S.r.l.
Inventor： Giorgio Mussi , Giacomo Langfelder , Carlo Valzasina , Gabriele Gattere
Abstract: In an embodiment, a clock generator has a variable-modulus frequency divider that receives a high-frequency clock signal and outputs a divided clock signal having a frequency controlled by a modulus-control signal generated by a temperature-compensation circuit. A jitter filter is coupled to the output of the variable-modulus frequency divider and to the temperature-compensation circuit and generates a compensated clock signal having switching edges that are delayed, with respect to the divided clock signal, by a time correlated to a quantization-error signal.
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