公开(公告)号：US20140344485A1

公开(公告)日：2014-11-20

申请号：US14278403

申请日：2014-05-15

Applicant: STMicroelectronics S.r.l.

Inventor： Mirko Dondini ,  Daniele Mangano ,  Giuseppe Falconeri

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A communication system is arranged to interface a plurality of transmission circuits with an interconnection network. Each transmission circuit generates read requests and/or write requests. The communication system includes a first circuit that operates independently of the communication protocol of the interconnection network. In particular, the first circuit includes, a) for each transmission circuit a communication interface configured for receiving the read requests and/or write requests from the respective transmission circuit, b) a segmentation circuit configured for dividing, i.e., segmenting, the read requests and/or write requests received from the transmission circuits into transfer segments, and c) an interleaving circuit configured for generating, via an operation of interleaving of the transfer segments, a series of segments. The communication system also includes a second circuit configured for converting the transfer segments of the series of segments into data packets according to the protocol of the interconnection network and for transmitting the data packets to the interconnection network.

Abstract translation: 通信系统被布置为将多个传输电路与互连网络接口。 每个传输电路产生读请求和/或写请求。 通信系统包括独立于互连网络的通信协议操作的第一电路。 特别地，第一电路包括：a）对于每个传输电路，配置用于从各个传输电路接收读取请求和/或写入请求的通信接口，b）分配电路，被配置为将读取请求 和/或将从所述传输电路接收的请求写入传输段，以及c）被配置为经由所述传送段的交织操作生成一系列段的交织电路。 通信系统还包括第二电路，其被配置为根据互连网络的协议将一系列段的传输段转换成数据包，并将数据包发送到互连网络。

公开(公告)号：US20140185390A1

公开(公告)日：2014-07-03

申请号：US14143383

申请日：2013-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Mangano ,  Salvatore Marco Rosselli ,  Giuseppe Falconeri

IPC: G11C7/10

CPC classification number: G11C7/1006 ,  G06F5/10 ,  G06F2205/106 ,  G06F2205/123

Abstract: A buffer for ordering out-of-order data includes a memory with a plurality of memory locations for temporarily storing data and a detection circuit configured for generating a control signal when the memory locations contain valid data. The detection circuit includes a first block configured for generating validity signals that identify the memory locations containing valid data and a search circuit configured for determining a search pointer as a function of the validity signals. In the case where each memory location contains valid data, the search pointer indicates the last memory location. In the case where at least one memory location is still free, the search pointer indicates the first memory location that is free.

Abstract translation: 用于排序无序数据的缓冲器包括具有用于临时存储数据的多个存储器位置的存储器和被配置为当存储器位置包含有效数据时生成控制信号的检测电路。 检测电路包括被配置用于产生识别包含有效数据的存储位置的有效信号的第一块和被配置为根据有效信号确定搜索指针的搜索电路。 在每个存储器位置包含有效数据的情况下，搜索指针指示最后的存储器位置。 在至少一个存储器位置仍然空闲的情况下，搜索指针指示第一存储器位置是空闲的。

公开(公告)号：US09471521B2

公开(公告)日：2016-10-18

申请号：US14278403

申请日：2014-05-15

Applicant: STMicroelectronics S.r.l.

Inventor： Mirko Dondini ,  Daniele Mangano ,  Giuseppe Falconeri

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A communication system is arranged to interface a plurality of transmission circuits with an interconnection network. Each transmission circuit generates read requests and/or write requests. The communication system includes a first circuit that operates independently of the communication protocol of the interconnection network. In particular, the first circuit includes, a) for each transmission circuit a communication interface configured for receiving the read requests and/or write requests from the respective transmission circuit, b) a segmentation circuit configured for dividing, i.e., segmenting, the read requests and/or write requests received from the transmission circuits into transfer segments, and c) an interleaving circuit configured for generating, via an operation of interleaving of the transfer segments, a series of segments. The communication system also includes a second circuit configured for converting the transfer segments of the series of segments into data packets according to the protocol of the interconnection network and for transmitting the data packets to the interconnection network.

Abstract translation: 通信系统被布置为将多个传输电路与互连网络接口。 每个传输电路产生读请求和/或写请求。 通信系统包括独立于互连网络的通信协议操作的第一电路。 特别地，第一电路包括：a）对于每个传输电路，配置用于从各个传输电路接收读取请求和/或写入请求的通信接口，b）分配电路，被配置为将读取请求 和/或将从所述传输电路接收的请求写入传输段，以及c）被配置为经由所述传送段的交织操作生成一系列段的交织电路。 通信系统还包括第二电路，其被配置为根据互连网络的协议将一系列段的传输段转换成数据包，并将数据包发送到互连网络。

公开(公告)号：US09093133B2

公开(公告)日：2015-07-28

申请号：US14143383

申请日：2013-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Mangano ,  Salvatore Marco Rosselli ,  Giuseppe Falconeri

IPC: G11C8/08 ,  G11C7/10 ,  G06F5/10

CPC classification number: G11C7/1006 ,  G06F5/10 ,  G06F2205/106 ,  G06F2205/123

Abstract: A buffer for ordering out-of-order data includes a memory with a plurality of memory locations for temporarily storing data and a detection circuit configured for generating a control signal when the memory locations contain valid data. The detection circuit includes a first block configured for generating validity signals that identify the memory locations containing valid data and a search circuit configured for determining a search pointer as a function of the validity signals. In the case where each memory location contains valid data, the search pointer indicates the last memory location. In the case where at least one memory location is still free, the search pointer indicates the first memory location that is free.

Abstract translation: 用于排序无序数据的缓冲器包括具有用于临时存储数据的多个存储器位置的存储器和被配置为当存储器位置包含有效数据时生成控制信号的检测电路。 检测电路包括被配置用于产生识别包含有效数据的存储位置的有效信号的第一块和被配置为根据有效信号确定搜索指针的搜索电路。 在每个存储器位置包含有效数据的情况下，搜索指针指示最后的存储器位置。 在至少一个存储器位置仍然空闲的情况下，搜索指针指示第一存储器位置是空闲的。